From ce2016bdc6fd52e708c4a1419c5d157dc5fb2cdb Mon Sep 17 00:00:00 2001
From: cephi_sui <cephi_sui@protonmail.com>
Date: Tue, 3 Dec 2024 22:16:08 -0500
Subject: [PATCH] pytorch analysis

---
 pytorch/analyze.py      |  189 ++++++
 pytorch/output.json     |  859 ++++++++++++++++++++++++
 pytorch/output_HPC.json | 1406 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 2454 insertions(+)
 create mode 100755 pytorch/analyze.py
 create mode 100644 pytorch/output.json
 create mode 100644 pytorch/output_HPC.json

diff --git a/pytorch/analyze.py b/pytorch/analyze.py
new file mode 100755
index 0000000..bf1c73d
--- /dev/null
+++ b/pytorch/analyze.py
@@ -0,0 +1,189 @@
+#! /bin/python3
+
+from perf_stat import Stat, CPU
+
+import argparse
+import os, glob
+import re
+import json
+
+from enum import Enum
+
+import math
+import numpy as np
+import matplotlib.pyplot as plt
+import itertools
+
+class Plot(Enum):
+    BOX = 'box'
+    LINE = 'line'
+
+def accumulate(stats_list: list[dict[str, str | int | float]], category: str, value: str):
+    print(category)
+    print(value)
+    category_list = np.array([stats[category] for stats in stats_list if value in stats])
+    value_list = np.array([stats[value] for stats in stats_list if value in stats])
+
+    result: dict[np.ndarray] = dict()
+    for category in np.sort(np.unique(category_list)):
+        result[category] = value_list[category_list == category]
+
+    return result
+
+def box_plot(ax, stats_list: list[dict[str, str | int | float]], x: Stat, y: Stat):
+    data: dict[str, np.ndarray] = accumulate(stats_list, x, y)
+
+    print("Plotted data: " + str(data))
+
+    ax.boxplot(data.values(), tick_labels=data.keys())
+    ax.set_ylabel(y.value)
+
+def line_plot(
+    ax, stats_list: list[dict[str, str | int | float]],
+    x: Stat, y: Stat, color: Stat
+):
+    x_data: dict[str, np.ndarray] = accumulate(stats_list, color, x)
+    y_data: dict[str, np.ndarray] = accumulate(stats_list, color, y)
+
+    for category in x_data.keys():
+        sorted_indices = np.argsort(x_data[category])
+        x_data[category] = x_data[category][sorted_indices]
+        y_data[category] = y_data[category][sorted_indices]
+        ax.plot(x_data[category], y_data[category], label=category)
+        print("Plotted x data: " + str(x_data[category]))
+        print("Plotted y data: " + str(y_data[category]))
+
+    ax.set_ylabel(y)
+    ax.grid(True)
+
+def visualize(
+    stats_list: list[dict[str, str | int | float]],
+    plot: Plot,
+    rows: int,
+    size_multiplier: int,
+    font_size: int,
+    x: Stat,
+    y: Stat,
+    color: Stat,
+    filter_list: list[str] = []
+):
+    # Remove stats entries containing undesired values (like a specific CPU).
+#    stats_list = [stats for stats in stats_list
+#                      if len([stats[key] for key in stats.keys()
+#                                        if stats[key] in filter_list]) == 0]
+
+    #x = Stat.MAXWELL_SIZE
+    #y = Stat.DTLB_MISS_RATE
+    #color = Stat.SOLVER
+
+    if y is None:
+        #ys = [stat for stat in Stat if stat.value in stats_list[0].keys()
+        ys = [stat for stat in stats_list[0].keys() if "power" not in stat]
+                                    #and stat is not x
+                                    #and y != color
+                                    #and y != marker
+                                    #and stat.value not in filter_list]
+        fig, axes = plt.subplots(rows, int(math.ceil(len(ys) / rows)),
+                                 figsize = (16 * size_multiplier, 9 * size_multiplier))
+        match plot:
+            case Plot.BOX:
+                for i, y in enumerate(ys):
+                    box_plot(axes[i % rows][int(i / rows)], stats_list, x, y)
+            case Plot.LINE:
+                for i, y in enumerate(ys):
+                    line_plot(axes[i % rows][int(i / rows)], stats_list, x, y, color)
+
+        handles, labels = axes[i % rows][int(i / rows)].get_legend_handles_labels()
+    else:
+        fig, ax = plt.subplots()
+
+        match plot:
+            case Plot.BOX:
+                box_plot(ax, stats_list, x, y)
+            case Plot.LINE:
+                line_plot(ax, stats_list, x, y, color)
+
+        handles, labels = ax.get_legend_handles_labels()
+
+    #box_plot(ax, stats, x, y)
+    #line_plot(ax, stats, x, y, color)
+
+    match plot:
+        case Plot.BOX:
+            title = f"{plot.value}_plot_of_{y.value.replace(' ', '_')}_vs_{x.value.replace(' ', '_')}_excluding_{filter_list}"
+        case Plot.LINE:
+            #title = f"{plot.value}_plot_of_{y.replace(' ', '_')}_vs_{x.replace(' ', '_')}_by_{color.replace(' ', '_')}_excluding_{filter_list}"
+            title = "altra_spmv"
+    fig.suptitle(title, fontsize = font_size)
+    fig.legend(handles, labels, fontsize = font_size)
+    fig.supxlabel(x, fontsize = font_size)
+
+    plt.savefig(title + ".png", dpi = 100)
+    plt.show()
+
+def main():
+    class Command(Enum):
+        PARSE = 'parse'
+        VISUALIZE = 'visualize'
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument('command', choices=[x.value for x in Command])
+    parser.add_argument('filepath',
+                        help='the output for the ' + Command.PARSE.value + ' command or the input for the ' + Command.VISUALIZE.value + ' command')
+    parser.add_argument('-i', '--input_dir',
+                        help='the input directory for the parse command')
+    parser.add_argument('-p', '--plot',
+                        choices=[x.name.lower() for x in Plot],
+                        help = 'the type of plot')
+    parser.add_argument('-r', '--rows', type=int,
+                        help = 'the number of rows to display when -y is not specified',
+                        default = 5)
+    parser.add_argument('-s', '--size', type=int,
+                        help = 'figure size multiplier',
+                        default = 4)
+    parser.add_argument('-fs', '--font_size', type=int,
+                        help = 'font size',
+                        default = 40)
+    parser.add_argument('-x',
+                        #choices=[x.name.lower() for x in Stat],
+                        help = 'the name of the x axis')
+    parser.add_argument('-y',
+                        #choices=[x.name.lower() for x in Stat],
+                        help = 'the name of the y axis')
+    parser.add_argument('-c', '--color',
+                        #choices=[x.name.lower() for x in Stat],
+                        help = 'the name of the color')
+    parser.add_argument('-f', '--filter', nargs = '+',
+                        help = 'a comma-separated string of names and values to filter out.',
+                        default = [])
+
+    args = parser.parse_args()
+
+    stats_list: list[dict] = list()
+    if args.command == Command.PARSE.value:
+        if (args.input_dir) is None:
+            print("An input directory is required with -i")
+            exit(-1)
+
+        for filename in glob.glob(f'{args.input_dir.rstrip("/")}/*.json'):
+            with open(filename, 'r') as file:
+                stats_list.append(json.load(file))
+            print(filename + " loaded.")
+
+        with open(args.filepath, 'w') as file:
+            json.dump(stats_list, file, indent = 2)
+
+    elif args.command == Command.VISUALIZE.value:
+        with open(args.filepath, 'r') as file:
+            stats_list = json.load(file)
+
+        #x = Stat[args.x.upper()] if args.x is not None else None
+        x = args.x
+        #y = Stat[args.y.upper()] if args.y is not None else None
+        y = args.y
+        #color = Stat[args.color.upper()] if args.color is not None else None
+        color = args.color
+        visualize(stats_list, Plot[args.plot.upper()], args.rows, args.size, args.font_size, x, y, color, args.filter)
+
+if __name__ == '__main__':
+    main()
diff --git a/pytorch/output.json b/pytorch/output.json
new file mode 100644
index 0000000..6948648
--- /dev/null
+++ b/pytorch/output.json
@@ -0,0 +1,859 @@
+[
+  {
+    "power_before": [
+      29.76,
+      33.16
+    ],
+    "shape": [
+      22687,
+      22687
+    ],
+    "nnz": 54705,
+    "% density": 0.00010628522108964806,
+    "time_s": 0.14322686195373535,
+    "power": [
+      22.6,
+      22.6,
+      26.16,
+      29.2
+    ],
+    "power_after": [
+      34.0,
+      30.16
+    ],
+    "task clock (msec)": 64.71,
+    "page faults": 3319,
+    "cycles": 57611295,
+    "instructions": 83148228,
+    "branch mispredictions": 318386,
+    "branches": 19233431,
+    "ITLB accesses": 27039805,
+    "ITLB misses": 6375,
+    "DTLB misses": 17290,
+    "DTLB accesses": 36688544,
+    "L1I cache accesses": 32508072,
+    "L1I cache misses": 297568,
+    "L1D cache misses": 477654,
+    "L1D cache accesses": 34044579,
+    "LL cache misses": 549474,
+    "LL cache accesses": 561939,
+    "L2D TLB accesses": 185622,
+    "L2D TLB misses": 23295,
+    "L2D cache misses": 305878,
+    "L2D cache accesses": 1763089,
+    "instructions per cycle": 1.4432626102225268,
+    "branch miss rate": 0.01655378075809771,
+    "ITLB miss rate": 0.00023576353453732377,
+    "DTLB miss rate": 0.00047126427257511227,
+    "L2D TLB miss rate": 0.12549697772893298,
+    "L1I cache miss rate": 0.009153664972810446,
+    "L1D cache miss rate": 0.014030251336049713,
+    "L2D cache miss rate": 0.17348982382625042,
+    "LL cache miss rate": 0.9778178770293573,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      20.48,
+      20.96
+    ],
+    "shape": [
+      24115,
+      24115
+    ],
+    "nnz": 116056,
+    "% density": 0.0001995689928120616,
+    "time_s": 0.3271017074584961,
+    "power": [
+      25.28,
+      26.08,
+      31.28,
+      32.96
+    ],
+    "power_after": [
+      33.4,
+      30.24
+    ],
+    "task clock (msec)": 59.88,
+    "page faults": 3313,
+    "cycles": 58169777,
+    "instructions": 57993431,
+    "branch mispredictions": 330494,
+    "branches": 20578427,
+    "ITLB accesses": 27982097,
+    "ITLB misses": 6614,
+    "DTLB misses": 17270,
+    "DTLB accesses": 37728899,
+    "L1I cache accesses": 29754926,
+    "L1I cache misses": 278786,
+    "L1D cache misses": 454742,
+    "L1D cache accesses": 31173246,
+    "LL cache misses": 543243,
+    "LL cache accesses": 560716,
+    "L2D TLB accesses": 162281,
+    "L2D TLB misses": 19847,
+    "L2D cache misses": 300577,
+    "L2D cache accesses": 1696278,
+    "instructions per cycle": 0.9969684257170179,
+    "branch miss rate": 0.016060216847478187,
+    "ITLB miss rate": 0.0002363654160729984,
+    "DTLB miss rate": 0.00045773930482307474,
+    "L2D TLB miss rate": 0.12230020766448321,
+    "L1I cache miss rate": 0.009369406598423401,
+    "L1D cache miss rate": 0.014587572946365611,
+    "L2D cache miss rate": 0.1771979592967662,
+    "LL cache miss rate": 0.9688380570556218,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      20.28,
+      20.32
+    ],
+    "shape": [
+      36692,
+      36692
+    ],
+    "nnz": 367662,
+    "% density": 0.0002730901120626302,
+    "time_s": 1.030203104019165,
+    "power": [
+      32.08,
+      47.84,
+      55.76,
+      58.08,
+      58.24
+    ],
+    "power_after": [
+      48.76,
+      45.16
+    ],
+    "task clock (msec)": 60.43,
+    "page faults": 3319,
+    "cycles": 66114448,
+    "instructions": 90786829,
+    "branch mispredictions": 341625,
+    "branches": 20129354,
+    "ITLB accesses": 27441303,
+    "ITLB misses": 6807,
+    "DTLB misses": 20551,
+    "DTLB accesses": 36867114,
+    "L1I cache accesses": 31744243,
+    "L1I cache misses": 271027,
+    "L1D cache misses": 464135,
+    "L1D cache accesses": 33441141,
+    "LL cache misses": 539935,
+    "LL cache accesses": 552519,
+    "L2D TLB accesses": 188291,
+    "L2D TLB misses": 24177,
+    "L2D cache misses": 301281,
+    "L2D cache accesses": 1737575,
+    "instructions per cycle": 1.3731768432824245,
+    "branch miss rate": 0.016971483535934636,
+    "ITLB miss rate": 0.00024805673404065397,
+    "DTLB miss rate": 0.0005574344658494288,
+    "L2D TLB miss rate": 0.12840231344036623,
+    "L1I cache miss rate": 0.008537831568388637,
+    "L1D cache miss rate": 0.01387916159918108,
+    "L2D cache miss rate": 0.17339165215889962,
+    "LL cache miss rate": 0.9772243126480719,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      50.88,
+      50.88
+    ],
+    "shape": [
+      11806,
+      11806
+    ],
+    "nnz": 65460,
+    "% density": 0.0004696458003979807,
+    "time_s": 0.1896660327911377,
+    "power": [
+      25.52,
+      32.28,
+      33.12,
+      33.12
+    ],
+    "power_after": [
+      32.88,
+      26.52
+    ],
+    "task clock (msec)": 42.01,
+    "page faults": 3263,
+    "cycles": 47084933,
+    "instructions": 77895119,
+    "branch mispredictions": 330923,
+    "branches": 19740519,
+    "ITLB accesses": 27761239,
+    "ITLB misses": 6471,
+    "DTLB misses": 17268,
+    "DTLB accesses": 36993265,
+    "L1I cache accesses": 31834980,
+    "L1I cache misses": 298333,
+    "L1D cache misses": 466901,
+    "L1D cache accesses": 33528976,
+    "LL cache misses": 525505,
+    "LL cache accesses": 546521,
+    "L2D TLB accesses": 184884,
+    "L2D TLB misses": 22933,
+    "L2D cache misses": 292367,
+    "L2D cache accesses": 1706226,
+    "instructions per cycle": 1.6543534000568716,
+    "branch miss rate": 0.016763642333821112,
+    "ITLB miss rate": 0.00023309478370183695,
+    "DTLB miss rate": 0.0004667876706746485,
+    "L2D TLB miss rate": 0.12403993855606758,
+    "L1I cache miss rate": 0.009371232524725947,
+    "L1D cache miss rate": 0.013925298523879763,
+    "L2D cache miss rate": 0.1713530329510862,
+    "LL cache miss rate": 0.9615458509371094,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      30.44,
+      35.52
+    ],
+    "shape": [
+      25181,
+      25181
+    ],
+    "nnz": 125750,
+    "% density": 0.00019831796057928155,
+    "time_s": 0.29622840881347656,
+    "power": [
+      23.84,
+      29.44,
+      33.0,
+      33.04
+    ],
+    "power_after": [
+      36.32,
+      30.0
+    ],
+    "task clock (msec)": 60.77,
+    "page faults": 3361,
+    "cycles": 63493475,
+    "instructions": 91578911,
+    "branch mispredictions": 329084,
+    "branches": 20406595,
+    "ITLB accesses": 26859919,
+    "ITLB misses": 6237,
+    "DTLB misses": 16689,
+    "DTLB accesses": 36348977,
+    "L1I cache accesses": 30979764,
+    "L1I cache misses": 292038,
+    "L1D cache misses": 469219,
+    "L1D cache accesses": 32411890,
+    "LL cache misses": 571870,
+    "LL cache accesses": 598306,
+    "L2D TLB accesses": 205488,
+    "L2D TLB misses": 26392,
+    "L2D cache misses": 342141,
+    "L2D cache accesses": 1857697,
+    "instructions per cycle": 1.442335783322617,
+    "branch miss rate": 0.01612635522976763,
+    "ITLB miss rate": 0.00023220472109390948,
+    "DTLB miss rate": 0.0004591325912693499,
+    "L2D TLB miss rate": 0.12843572374055906,
+    "L1I cache miss rate": 0.009426734173959492,
+    "L1D cache miss rate": 0.014476755289494072,
+    "L2D cache miss rate": 0.1841748142996409,
+    "LL cache miss rate": 0.9558152517273769,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      30.48,
+      33.04
+    ],
+    "shape": [
+      131828,
+      131828
+    ],
+    "nnz": 841372,
+    "% density": 4.841419648464106e-05,
+    "time_s": 2.848874092102051,
+    "power": [
+      65.52,
+      75.88,
+      71.16,
+      71.16,
+      59.72,
+      47.92,
+      48.68
+    ],
+    "power_after": [
+      68.68,
+      67.88
+    ],
+    "task clock (msec)": 49.87,
+    "page faults": 3300,
+    "cycles": 51935476,
+    "instructions": 83731856,
+    "branch mispredictions": 326464,
+    "branches": 20341367,
+    "ITLB accesses": 27590154,
+    "ITLB misses": 6210,
+    "DTLB misses": 17536,
+    "DTLB accesses": 36763243,
+    "L1I cache accesses": 31663300,
+    "L1I cache misses": 289727,
+    "L1D cache misses": 462864,
+    "L1D cache accesses": 33262254,
+    "LL cache misses": 530272,
+    "LL cache accesses": 551373,
+    "L2D TLB accesses": 196152,
+    "L2D TLB misses": 23542,
+    "L2D cache misses": 301998,
+    "L2D cache accesses": 1732662,
+    "instructions per cycle": 1.6122285275675532,
+    "branch miss rate": 0.01604926551888081,
+    "ITLB miss rate": 0.000225080294948698,
+    "DTLB miss rate": 0.0004769981799483794,
+    "L2D TLB miss rate": 0.12001916880786329,
+    "L1I cache miss rate": 0.00915024649989104,
+    "L1D cache miss rate": 0.013915593332911234,
+    "L2D cache miss rate": 0.17429712200071334,
+    "LL cache miss rate": 0.9617300810884828,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      20.44,
+      20.2
+    ],
+    "shape": [
+      24818,
+      24818
+    ],
+    "nnz": 239978,
+    "% density": 0.00038961697406616504,
+    "time_s": 0.556269645690918,
+    "power": [
+      25.24,
+      32.16,
+      33.0,
+      32.52
+    ],
+    "power_after": [
+      34.24,
+      30.28
+    ],
+    "task clock (msec)": 62.49,
+    "page faults": 3312,
+    "cycles": 76783170,
+    "instructions": 77095702,
+    "branch mispredictions": 323514,
+    "branches": 19769937,
+    "ITLB accesses": 26809325,
+    "ITLB misses": 6925,
+    "DTLB misses": 19003,
+    "DTLB accesses": 36516965,
+    "L1I cache accesses": 31104231,
+    "L1I cache misses": 285499,
+    "L1D cache misses": 468498,
+    "L1D cache accesses": 32677465,
+    "LL cache misses": 559358,
+    "LL cache accesses": 571935,
+    "L2D TLB accesses": 194840,
+    "L2D TLB misses": 23481,
+    "L2D cache misses": 313487,
+    "L2D cache accesses": 1779730,
+    "instructions per cycle": 1.004070319055595,
+    "branch miss rate": 0.016363936819829016,
+    "ITLB miss rate": 0.00025830564551699827,
+    "DTLB miss rate": 0.0005203882633729282,
+    "L2D TLB miss rate": 0.12051426811742968,
+    "L1I cache miss rate": 0.009178783426601994,
+    "L1D cache miss rate": 0.01433703624194839,
+    "L2D cache miss rate": 0.1761430104566423,
+    "LL cache miss rate": 0.9780097388689274,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      16.52,
+      16.64
+    ],
+    "shape": [
+      81871,
+      81871
+    ],
+    "nnz": 545671,
+    "% density": 8.140867447881048e-05,
+    "time_s": 1.3372814655303955,
+    "power": [
+      23.92,
+      38.6,
+      46.04,
+      48.2,
+      48.2
+    ],
+    "power_after": [
+      45.0,
+      44.08
+    ],
+    "task clock (msec)": 59.01,
+    "page faults": 3448,
+    "cycles": 73062796,
+    "instructions": 88329175,
+    "branch mispredictions": 331091,
+    "branches": 20013316,
+    "ITLB accesses": 26330936,
+    "ITLB misses": 5193,
+    "DTLB misses": 16837,
+    "DTLB accesses": 35930477,
+    "L1I cache accesses": 31853890,
+    "L1I cache misses": 306147,
+    "L1D cache misses": 479933,
+    "L1D cache accesses": 33426019,
+    "LL cache misses": 540302,
+    "LL cache accesses": 553181,
+    "L2D TLB accesses": 173206,
+    "L2D TLB misses": 21390,
+    "L2D cache misses": 300032,
+    "L2D cache accesses": 1739931,
+    "instructions per cycle": 1.2089487377406143,
+    "branch miss rate": 0.016543535314187813,
+    "ITLB miss rate": 0.0001972204861991993,
+    "DTLB miss rate": 0.000468599401004334,
+    "L2D TLB miss rate": 0.12349456716280037,
+    "L1I cache miss rate": 0.009610976869701,
+    "L1D cache miss rate": 0.014358066391334247,
+    "L2D cache miss rate": 0.17243902200719455,
+    "LL cache miss rate": 0.9767182893121781,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      50.68,
+      49.4
+    ],
+    "shape": [
+      10879,
+      10879
+    ],
+    "nnz": 39994,
+    "% density": 0.0003379223282393842,
+    "time_s": 0.11296772956848145,
+    "power": [
+      26.2,
+      29.76,
+      33.64,
+      34.44
+    ],
+    "power_after": [
+      36.84,
+      29.44
+    ],
+    "task clock (msec)": 67.56,
+    "page faults": 3829,
+    "cycles": 47862000,
+    "instructions": 84392375,
+    "branch mispredictions": 331622,
+    "branches": 19800140,
+    "ITLB accesses": 25905045,
+    "ITLB misses": 6746,
+    "DTLB misses": 17547,
+    "DTLB accesses": 35220079,
+    "L1I cache accesses": 30359576,
+    "L1I cache misses": 283204,
+    "L1D cache misses": 465520,
+    "L1D cache accesses": 31843274,
+    "LL cache misses": 560542,
+    "LL cache accesses": 575610,
+    "L2D TLB accesses": 173643,
+    "L2D TLB misses": 21499,
+    "L2D cache misses": 313335,
+    "L2D cache accesses": 1741621,
+    "instructions per cycle": 1.7632438051063475,
+    "branch miss rate": 0.016748467435078743,
+    "ITLB miss rate": 0.0002604125953072075,
+    "DTLB miss rate": 0.0004982101261044871,
+    "L2D TLB miss rate": 0.12381149830399152,
+    "L1I cache miss rate": 0.009328325270418797,
+    "L1D cache miss rate": 0.014619099782264852,
+    "L2D cache miss rate": 0.17990998041479747,
+    "LL cache miss rate": 0.9738225534650197,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      53.64,
+      46.88
+    ],
+    "shape": [
+      82144,
+      82144
+    ],
+    "nnz": 549202,
+    "% density": 8.13917555860553e-05,
+    "time_s": 1.2292509078979492,
+    "power": [
+      40.64,
+      52.44,
+      54.8,
+      54.96,
+      46.8
+    ],
+    "power_after": [
+      47.88,
+      47.08
+    ],
+    "task clock (msec)": 61.26,
+    "page faults": 3303,
+    "cycles": 44515786,
+    "instructions": 81513738,
+    "branch mispredictions": 328019,
+    "branches": 19893662,
+    "ITLB accesses": 27248112,
+    "ITLB misses": 5792,
+    "DTLB misses": 16632,
+    "DTLB accesses": 36929042,
+    "L1I cache accesses": 31702830,
+    "L1I cache misses": 295778,
+    "L1D cache misses": 470423,
+    "L1D cache accesses": 33155119,
+    "LL cache misses": 545220,
+    "LL cache accesses": 562139,
+    "L2D TLB accesses": 192206,
+    "L2D TLB misses": 24891,
+    "L2D cache misses": 307033,
+    "L2D cache accesses": 1782260,
+    "instructions per cycle": 1.8311198189334452,
+    "branch miss rate": 0.01648861833482443,
+    "ITLB miss rate": 0.0002125651861677609,
+    "DTLB miss rate": 0.0004503772396803578,
+    "L2D TLB miss rate": 0.12950168048864238,
+    "L1I cache miss rate": 0.009329703373484323,
+    "L1D cache miss rate": 0.014188548079106578,
+    "L2D cache miss rate": 0.17227172241984895,
+    "LL cache miss rate": 0.9699024618466251,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      34.04,
+      43.96
+    ],
+    "shape": [
+      32580,
+      32580
+    ],
+    "nnz": 155598,
+    "% density": 0.00014658915806621921,
+    "time_s": 0.4164857864379883,
+    "power": [
+      23.72,
+      23.72,
+      29.88,
+      33.32
+    ],
+    "power_after": [
+      33.36,
+      32.52
+    ],
+    "task clock (msec)": 61.63,
+    "page faults": 3304,
+    "cycles": 64734203,
+    "instructions": 53597991,
+    "branch mispredictions": 330777,
+    "branches": 20357034,
+    "ITLB accesses": 27381387,
+    "ITLB misses": 6248,
+    "DTLB misses": 17636,
+    "DTLB accesses": 37436110,
+    "L1I cache accesses": 32505993,
+    "L1I cache misses": 303849,
+    "L1D cache misses": 467426,
+    "L1D cache accesses": 34241110,
+    "LL cache misses": 550075,
+    "LL cache accesses": 562829,
+    "L2D TLB accesses": 199285,
+    "L2D TLB misses": 24424,
+    "L2D cache misses": 310155,
+    "L2D cache accesses": 1783824,
+    "instructions per cycle": 0.8279701999266138,
+    "branch miss rate": 0.016248781625063848,
+    "ITLB miss rate": 0.00022818420410916364,
+    "DTLB miss rate": 0.00047109595521543235,
+    "L2D TLB miss rate": 0.12255814536969667,
+    "L1I cache miss rate": 0.009347476325365603,
+    "L1D cache miss rate": 0.01365101773861887,
+    "L2D cache miss rate": 0.17387085272986572,
+    "LL cache miss rate": 0.9773394761108614,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      16.32,
+      16.2
+    ],
+    "shape": [
+      116835,
+      116835
+    ],
+    "nnz": 766396,
+    "% density": 5.614451099680581e-05,
+    "time_s": 2.2665774822235107,
+    "power": [
+      35.16,
+      50.8,
+      53.4,
+      53.4,
+      46.08,
+      46.88
+    ],
+    "power_after": [
+      58.4,
+      57.32
+    ],
+    "task clock (msec)": 50.43,
+    "page faults": 3285,
+    "cycles": 54118679,
+    "instructions": 77692421,
+    "branch mispredictions": 325039,
+    "branches": 19383216,
+    "ITLB accesses": 26060519,
+    "ITLB misses": 4749,
+    "DTLB misses": 16865,
+    "DTLB accesses": 34819729,
+    "L1I cache accesses": 30777115,
+    "L1I cache misses": 293980,
+    "L1D cache misses": 461522,
+    "L1D cache accesses": 32216597,
+    "LL cache misses": 567700,
+    "LL cache accesses": 588689,
+    "L2D TLB accesses": 189417,
+    "L2D TLB misses": 22360,
+    "L2D cache misses": 328306,
+    "L2D cache accesses": 1908607,
+    "instructions per cycle": 1.4355934482436277,
+    "branch miss rate": 0.0167690954896236,
+    "ITLB miss rate": 0.00018222967854170517,
+    "DTLB miss rate": 0.00048435184547243316,
+    "L2D TLB miss rate": 0.11804642666708902,
+    "L1I cache miss rate": 0.009551902444397404,
+    "L1D cache miss rate": 0.014325597455249542,
+    "L2D cache miss rate": 0.172013410827897,
+    "LL cache miss rate": 0.9643461997761127,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      20.16,
+      20.08
+    ],
+    "shape": [
+      31379,
+      31379
+    ],
+    "nnz": 106762,
+    "% density": 0.00010842726485909405,
+    "time_s": 0.336850643157959,
+    "power": [
+      24.28,
+      30.72,
+      30.72,
+      34.56
+    ],
+    "power_after": [
+      37.32,
+      32.92
+    ],
+    "task clock (msec)": 60.78,
+    "page faults": 3300,
+    "cycles": 66733059,
+    "instructions": 87889334,
+    "branch mispredictions": 326300,
+    "branches": 19832700,
+    "ITLB accesses": 27233629,
+    "ITLB misses": 5868,
+    "DTLB misses": 16893,
+    "DTLB accesses": 36409508,
+    "L1I cache accesses": 30924532,
+    "L1I cache misses": 288199,
+    "L1D cache misses": 462816,
+    "L1D cache accesses": 32428375,
+    "LL cache misses": 551997,
+    "LL cache accesses": 568528,
+    "L2D TLB accesses": 193991,
+    "L2D TLB misses": 24353,
+    "L2D cache misses": 312207,
+    "L2D cache accesses": 1821196,
+    "instructions per cycle": 1.3170284011707,
+    "branch miss rate": 0.016452626218316214,
+    "ITLB miss rate": 0.0002154688969288669,
+    "DTLB miss rate": 0.00046397221297250155,
+    "L2D TLB miss rate": 0.125536751704976,
+    "L1I cache miss rate": 0.009319429635992551,
+    "L1D cache miss rate": 0.014271945479845968,
+    "L2D cache miss rate": 0.17142965391973186,
+    "LL cache miss rate": 0.9709231559395491,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      20.56,
+      20.28
+    ],
+    "shape": [
+      36682,
+      36682
+    ],
+    "nnz": 88328,
+    "% density": 6.564359899804003e-05,
+    "time_s": 0.30861377716064453,
+    "power": [
+      23.88,
+      27.6,
+      39.8,
+      40.12
+    ],
+    "power_after": [
+      39.28,
+      35.2
+    ],
+    "task clock (msec)": 65.91,
+    "page faults": 3247,
+    "cycles": 92293071,
+    "instructions": 76208632,
+    "branch mispredictions": 320083,
+    "branches": 19285106,
+    "ITLB accesses": 26853940,
+    "ITLB misses": 6728,
+    "DTLB misses": 13955,
+    "DTLB accesses": 37111059,
+    "L1I cache accesses": 32554796,
+    "L1I cache misses": 298729,
+    "L1D cache misses": 473779,
+    "L1D cache accesses": 34117102,
+    "LL cache misses": 535040,
+    "LL cache accesses": 547502,
+    "L2D TLB accesses": 179876,
+    "L2D TLB misses": 21809,
+    "L2D cache misses": 298620,
+    "L2D cache accesses": 1722959,
+    "instructions per cycle": 0.8257243059990929,
+    "branch miss rate": 0.016597419791210898,
+    "ITLB miss rate": 0.0002505405165871377,
+    "DTLB miss rate": 0.0003760334621547717,
+    "L2D TLB miss rate": 0.12124463519313304,
+    "L1I cache miss rate": 0.009176190199440968,
+    "L1D cache miss rate": 0.013886847716432655,
+    "L2D cache miss rate": 0.17331811145825293,
+    "LL cache miss rate": 0.9772384393116372,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      34.6,
+      37.16
+    ],
+    "shape": [
+      115406,
+      115406
+    ],
+    "nnz": 572066,
+    "% density": 4.295259032005559e-05,
+    "time_s": 1.0817186832427979,
+    "power": [
+      34.32,
+      50.84,
+      52.12,
+      52.4,
+      52.76
+    ],
+    "power_after": [
+      49.0,
+      45.08
+    ],
+    "task clock (msec)": 60.55,
+    "page faults": 3490,
+    "cycles": 49977496,
+    "instructions": 78622993,
+    "branch mispredictions": 327078,
+    "branches": 20135808,
+    "ITLB accesses": 27608093,
+    "ITLB misses": 6616,
+    "DTLB misses": 17185,
+    "DTLB accesses": 36866957,
+    "L1I cache accesses": 32639204,
+    "L1I cache misses": 309643,
+    "L1D cache misses": 478856,
+    "L1D cache accesses": 34280618,
+    "LL cache misses": 555275,
+    "LL cache accesses": 578455,
+    "L2D TLB accesses": 188723,
+    "L2D TLB misses": 24635,
+    "L2D cache misses": 319663,
+    "L2D cache accesses": 1799940,
+    "instructions per cycle": 1.573167911413569,
+    "branch miss rate": 0.016243599462211798,
+    "ITLB miss rate": 0.00023963987661154286,
+    "DTLB miss rate": 0.00046613556958335347,
+    "L2D TLB miss rate": 0.13053522888042263,
+    "L1I cache miss rate": 0.009486842877663316,
+    "L1D cache miss rate": 0.013968709665619214,
+    "L2D cache miss rate": 0.17759647543807017,
+    "LL cache miss rate": 0.9599277385449171,
+    "architecture": "altra"
+  },
+  {
+    "power_before": [
+      16.52,
+      16.24
+    ],
+    "shape": [
+      26518,
+      26518
+    ],
+    "nnz": 65369,
+    "% density": 9.295875717624285e-05,
+    "time_s": 0.1715233325958252,
+    "power": [
+      18.56,
+      24.92,
+      27.84,
+      27.84
+    ],
+    "power_after": [
+      33.2,
+      27.28
+    ],
+    "task clock (msec)": 61.92,
+    "page faults": 3281,
+    "cycles": 66250810,
+    "instructions": 75178179,
+    "branch mispredictions": 332366,
+    "branches": 19076182,
+    "ITLB accesses": 27005133,
+    "ITLB misses": 4791,
+    "DTLB misses": 13403,
+    "DTLB accesses": 36457054,
+    "L1I cache accesses": 32367686,
+    "L1I cache misses": 287524,
+    "L1D cache misses": 467557,
+    "L1D cache accesses": 34022862,
+    "LL cache misses": 535707,
+    "LL cache accesses": 556316,
+    "L2D TLB accesses": 150149,
+    "L2D TLB misses": 18418,
+    "L2D cache misses": 297042,
+    "L2D cache accesses": 1687364,
+    "instructions per cycle": 1.1347510920998551,
+    "branch miss rate": 0.017423088121092577,
+    "ITLB miss rate": 0.00017741071669597036,
+    "DTLB miss rate": 0.00036763804338112453,
+    "L2D TLB miss rate": 0.12266481961251822,
+    "L1I cache miss rate": 0.008883057009388932,
+    "L1D cache miss rate": 0.013742435895016709,
+    "L2D cache miss rate": 0.1760390763344483,
+    "LL cache miss rate": 0.9629545078696281,
+    "architecture": "altra"
+  }
+]
\ No newline at end of file
diff --git a/pytorch/output_HPC.json b/pytorch/output_HPC.json
new file mode 100644
index 0000000..9be58d5
--- /dev/null
+++ b/pytorch/output_HPC.json
@@ -0,0 +1,1406 @@
+[
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      80.64,
+      75.2,
+      61.4,
+      49.84,
+      38.12,
+      38.12,
+      24.16,
+      22.68,
+      22.36,
+      22.2
+    ],
+    "matrix": "ASIC_680k",
+    "shape": [
+      682862,
+      682862
+    ],
+    "nnz": 3871773,
+    "% density": 8.303171256088674e-06,
+    "time_s": 41.51614689826965,
+    "power": [
+      92.4,
+      92.44,
+      84.28,
+      73.04,
+      59.64,
+      53.28,
+      56.32,
+      65.88,
+      80.28,
+      93.76,
+      96.16,
+      94.44,
+      94.44,
+      94.2,
+      93.92,
+      92.48,
+      92.16,
+      91.84,
+      92.08,
+      91.84,
+      91.68,
+      90.68,
+      90.88,
+      90.28,
+      90.28,
+      92.44,
+      92.52,
+      92.84,
+      90.0,
+      89.64,
+      88.16,
+      87.28,
+      88.12,
+      88.24,
+      88.08,
+      85.72,
+      85.12,
+      85.12,
+      81.72,
+      82.52,
+      83.84,
+      86.32,
+      88.8,
+      91.0,
+      90.2
+    ],
+    "power_after": [
+      21.92,
+      21.88,
+      21.92,
+      21.88,
+      21.88,
+      21.72,
+      21.72,
+      21.72,
+      21.72,
+      21.44
+    ],
+    "task clock (msec)": 55.74,
+    "page faults": 3266,
+    "cycles": 51085608,
+    "instructions": 88049969,
+    "branch mispredictions": 332704,
+    "branches": 20219525,
+    "ITLB accesses": 27856157,
+    "ITLB misses": 6496,
+    "DTLB misses": 17046,
+    "DTLB accesses": 37522360,
+    "L1I cache accesses": 31475230,
+    "L1I cache misses": 277921,
+    "L1D cache misses": 462005,
+    "L1D cache accesses": 33126938,
+    "LL cache misses": 558923,
+    "LL cache accesses": 571263,
+    "L2D TLB accesses": 190627,
+    "L2D TLB misses": 24234,
+    "L2D cache misses": 314815,
+    "L2D cache accesses": 1760110,
+    "instructions per cycle": 1.7235768046452535,
+    "branch miss rate": 0.01645459030318467,
+    "ITLB miss rate": 0.00023319799640704206,
+    "DTLB miss rate": 0.0004542891225392006,
+    "L2D TLB miss rate": 0.12712784652751186,
+    "L1I cache miss rate": 0.008829832220447635,
+    "L1D cache miss rate": 0.013946504805243395,
+    "L2D cache miss rate": 0.17886098027964162,
+    "LL cache miss rate": 0.978398741035215,
+    "size": 466300511044
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      31.36,
+      30.64,
+      31.12,
+      24.52,
+      24.16,
+      23.12,
+      22.08,
+      21.28,
+      21.16,
+      20.88
+    ],
+    "matrix": "rma10",
+    "shape": [
+      46835,
+      46835
+    ],
+    "nnz": 2374001,
+    "% density": 0.0010822805369125833,
+    "time_s": 68.86891412734985,
+    "power": [
+      81.8,
+      81.32,
+      75.08,
+      63.48,
+      51.92,
+      51.96,
+      51.8,
+      65.0,
+      65.0,
+      75.12,
+      82.68,
+      82.32,
+      82.08,
+      82.76,
+      82.8,
+      83.6,
+      83.36,
+      83.08,
+      82.88,
+      83.0,
+      83.32,
+      83.32,
+      83.36,
+      84.64,
+      84.56,
+      84.24,
+      83.52,
+      83.4,
+      83.36,
+      83.36,
+      83.72,
+      84.16,
+      83.24,
+      82.76,
+      82.76,
+      82.96,
+      82.36,
+      82.24,
+      81.64,
+      81.6,
+      81.4,
+      81.6,
+      81.88,
+      82.32,
+      83.04,
+      83.48,
+      83.48,
+      84.32,
+      84.04,
+      84.32,
+      83.16,
+      82.44,
+      81.96,
+      81.4,
+      81.8,
+      82.08,
+      81.8,
+      81.84,
+      82.04,
+      82.04,
+      82.08,
+      82.44,
+      82.6,
+      82.84,
+      83.8,
+      84.24,
+      84.6,
+      85.4,
+      85.6,
+      86.0,
+      85.72,
+      85.36
+    ],
+    "power_after": [
+      21.96,
+      21.88,
+      21.96,
+      21.96,
+      22.0,
+      21.68,
+      21.44,
+      21.16,
+      21.04,
+      20.92
+    ],
+    "task clock (msec)": 58.3,
+    "page faults": 3281,
+    "cycles": 81319364,
+    "instructions": 90830397,
+    "branch mispredictions": 342237,
+    "branches": 20641135,
+    "ITLB accesses": 27974213,
+    "ITLB misses": 6660,
+    "DTLB misses": 18441,
+    "DTLB accesses": 37780346,
+    "L1I cache accesses": 31166891,
+    "L1I cache misses": 291301,
+    "L1D cache misses": 477186,
+    "L1D cache accesses": 32682323,
+    "LL cache misses": 538552,
+    "LL cache accesses": 552543,
+    "L2D TLB accesses": 202351,
+    "L2D TLB misses": 24178,
+    "L2D cache misses": 298051,
+    "L2D cache accesses": 1775481,
+    "instructions per cycle": 1.1169590185186398,
+    "branch miss rate": 0.01658033824205888,
+    "ITLB miss rate": 0.00023807640272132053,
+    "DTLB miss rate": 0.00048811093471722044,
+    "L2D TLB miss rate": 0.11948544855226809,
+    "L1I cache miss rate": 0.00934648887500521,
+    "L1D cache miss rate": 0.014600736918241704,
+    "L2D cache miss rate": 0.1678705657790762,
+    "LL cache miss rate": 0.9746788937693537,
+    "size": 2193517225
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      16.44,
+      16.44,
+      16.44,
+      16.84,
+      16.72,
+      16.6,
+      16.72,
+      16.84,
+      16.68,
+      16.84
+    ],
+    "matrix": "p2p-Gnutella30",
+    "shape": [
+      36682,
+      36682
+    ],
+    "nnz": 88328,
+    "% density": 6.564359899804003e-05,
+    "time_s": 2.896674871444702,
+    "power": [
+      56.32,
+      68.24,
+      71.76,
+      59.48,
+      47.6,
+      48.76,
+      52.6
+    ],
+    "power_after": [
+      16.92,
+      17.0,
+      16.96,
+      16.8,
+      16.48,
+      16.52,
+      16.52,
+      16.52,
+      16.24,
+      16.36
+    ],
+    "task clock (msec)": 56.47,
+    "page faults": 3222,
+    "cycles": 69105836,
+    "instructions": 89065155,
+    "branch mispredictions": 333669,
+    "branches": 20078755,
+    "ITLB accesses": 26015038,
+    "ITLB misses": 5212,
+    "DTLB misses": 17039,
+    "DTLB accesses": 35296010,
+    "L1I cache accesses": 31837486,
+    "L1I cache misses": 293353,
+    "L1D cache misses": 462358,
+    "L1D cache accesses": 33478540,
+    "LL cache misses": 546516,
+    "LL cache accesses": 559865,
+    "L2D TLB accesses": 190400,
+    "L2D TLB misses": 23787,
+    "L2D cache misses": 307032,
+    "L2D cache accesses": 1768186,
+    "instructions per cycle": 1.288822480926213,
+    "branch miss rate": 0.016618012421586895,
+    "ITLB miss rate": 0.00020034566161310238,
+    "DTLB miss rate": 0.00048274578344691083,
+    "L2D TLB miss rate": 0.12493172268907562,
+    "L1I cache miss rate": 0.009214075508348869,
+    "L1D cache miss rate": 0.013810578358554464,
+    "L2D cache miss rate": 0.17364236567872385,
+    "LL cache miss rate": 0.9761567520741607,
+    "size": 1345569124
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      32.08,
+      31.8,
+      28.68,
+      27.6,
+      22.96,
+      22.08,
+      21.0,
+      20.84,
+      20.68,
+      20.72
+    ],
+    "matrix": "va2010",
+    "shape": [
+      285762,
+      285762
+    ],
+    "nnz": 1402128,
+    "% density": 1.717033263003816e-05,
+    "time_s": 14.632386922836304,
+    "power": [
+      85.16,
+      83.48,
+      76.96,
+      67.44,
+      54.04,
+      51.4,
+      54.24,
+      66.76,
+      83.2,
+      96.44,
+      96.44,
+      95.84,
+      94.24,
+      92.36,
+      91.2,
+      89.32,
+      87.48,
+      88.68,
+      88.24
+    ],
+    "power_after": [
+      21.12,
+      21.0,
+      21.16,
+      21.4,
+      21.32,
+      21.36,
+      21.36,
+      21.12,
+      20.76,
+      20.84
+    ],
+    "task clock (msec)": 57.32,
+    "page faults": 3280,
+    "cycles": 39497791,
+    "instructions": 64385555,
+    "branch mispredictions": 332792,
+    "branches": 19983954,
+    "ITLB accesses": 27156853,
+    "ITLB misses": 6466,
+    "DTLB misses": 18244,
+    "DTLB accesses": 36466301,
+    "L1I cache accesses": 30929971,
+    "L1I cache misses": 291811,
+    "L1D cache misses": 473063,
+    "L1D cache accesses": 32462905,
+    "LL cache misses": 544953,
+    "LL cache accesses": 565172,
+    "L2D TLB accesses": 183225,
+    "L2D TLB misses": 23924,
+    "L2D cache misses": 301362,
+    "L2D cache accesses": 1756590,
+    "instructions per cycle": 1.6301052127193645,
+    "branch miss rate": 0.01665296067034582,
+    "ITLB miss rate": 0.00023809828038616994,
+    "DTLB miss rate": 0.000500297521264907,
+    "L2D TLB miss rate": 0.13057170145995362,
+    "L1I cache miss rate": 0.009434570759862659,
+    "L1D cache miss rate": 0.014572417348354991,
+    "L2D cache miss rate": 0.17156080815671274,
+    "LL cache miss rate": 0.964225050073252,
+    "size": 81659920644
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      16.6,
+      16.64,
+      17.04,
+      17.08,
+      16.92,
+      17.24,
+      16.88,
+      16.36,
+      16.4,
+      16.4
+    ],
+    "matrix": "ri2010",
+    "shape": [
+      25181,
+      25181
+    ],
+    "nnz": 125750,
+    "% density": 0.00019831796057928155,
+    "time_s": 2.970583200454712,
+    "power": [
+      23.04,
+      23.28,
+      23.76,
+      24.12,
+      21.4,
+      26.28,
+      26.36
+    ],
+    "power_after": [
+      16.16,
+      16.16,
+      16.52,
+      16.48,
+      16.52,
+      16.44,
+      16.36,
+      16.48,
+      16.76,
+      16.6
+    ],
+    "task clock (msec)": 52.61,
+    "page faults": 3292,
+    "cycles": 42915672,
+    "instructions": 71002596,
+    "branch mispredictions": 344300,
+    "branches": 20224759,
+    "ITLB accesses": 26039851,
+    "ITLB misses": 5035,
+    "DTLB misses": 16402,
+    "DTLB accesses": 34820806,
+    "L1I cache accesses": 31878105,
+    "L1I cache misses": 299057,
+    "L1D cache misses": 471869,
+    "L1D cache accesses": 33450518,
+    "LL cache misses": 530093,
+    "LL cache accesses": 551126,
+    "L2D TLB accesses": 188315,
+    "L2D TLB misses": 22856,
+    "L2D cache misses": 299885,
+    "L2D cache accesses": 1763155,
+    "instructions per cycle": 1.6544677664607,
+    "branch miss rate": 0.01702368863826758,
+    "ITLB miss rate": 0.00019335748119296073,
+    "DTLB miss rate": 0.0004710402165877493,
+    "L2D TLB miss rate": 0.12137110692191275,
+    "L1I cache miss rate": 0.009381266546427399,
+    "L1D cache miss rate": 0.014106478111938357,
+    "L2D cache miss rate": 0.1700843090936418,
+    "LL cache miss rate": 0.9618363132931489,
+    "size": 634082761
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      30.08,
+      25.12,
+      24.68,
+      23.68,
+      22.84,
+      21.96,
+      21.08,
+      20.96,
+      20.8,
+      20.96
+    ],
+    "matrix": "p2p-Gnutella04",
+    "shape": [
+      10879,
+      10879
+    ],
+    "nnz": 39994,
+    "% density": 0.0003379223282393842,
+    "time_s": 0.9992897510528564,
+    "power": [
+      29.48,
+      30.52,
+      31.88,
+      31.24,
+      34.32
+    ],
+    "power_after": [
+      20.4,
+      20.6,
+      20.64,
+      20.76,
+      20.92,
+      20.84,
+      20.88,
+      20.88,
+      20.88,
+      20.84
+    ],
+    "task clock (msec)": 52.68,
+    "page faults": 3272,
+    "cycles": 63019732,
+    "instructions": 73518898,
+    "branch mispredictions": 333423,
+    "branches": 19435905,
+    "ITLB accesses": 27447537,
+    "ITLB misses": 6417,
+    "DTLB misses": 18300,
+    "DTLB accesses": 37569384,
+    "L1I cache accesses": 30830481,
+    "L1I cache misses": 290545,
+    "L1D cache misses": 473875,
+    "L1D cache accesses": 32284772,
+    "LL cache misses": 529403,
+    "LL cache accesses": 549794,
+    "L2D TLB accesses": 198306,
+    "L2D TLB misses": 24497,
+    "L2D cache misses": 298519,
+    "L2D cache accesses": 1772795,
+    "instructions per cycle": 1.1666012480027683,
+    "branch miss rate": 0.017155002558409294,
+    "ITLB miss rate": 0.00023379146915805232,
+    "DTLB miss rate": 0.000487098750408045,
+    "L2D TLB miss rate": 0.12353131019737174,
+    "L1I cache miss rate": 0.009423952873132274,
+    "L1D cache miss rate": 0.014677972636758903,
+    "L2D cache miss rate": 0.16838890001381998,
+    "LL cache miss rate": 0.9629115632400499,
+    "size": 118352641
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      22.08,
+      21.88,
+      21.88,
+      21.88,
+      21.56,
+      21.64,
+      21.84,
+      21.88,
+      21.72,
+      21.92
+    ],
+    "matrix": "de2010",
+    "shape": [
+      24115,
+      24115
+    ],
+    "nnz": 116056,
+    "% density": 0.0001995689928120616,
+    "time_s": 2.7533018589019775,
+    "power": [
+      29.48,
+      30.24,
+      27.96,
+      28.4,
+      26.84,
+      30.6,
+      30.92
+    ],
+    "power_after": [
+      20.84,
+      21.24,
+      21.2,
+      21.24,
+      21.28,
+      20.88,
+      20.68,
+      20.56,
+      20.52,
+      20.56
+    ],
+    "task clock (msec)": 61.38,
+    "page faults": 3315,
+    "cycles": 65013274,
+    "instructions": 87442627,
+    "branch mispredictions": 328392,
+    "branches": 19496396,
+    "ITLB accesses": 28311619,
+    "ITLB misses": 6963,
+    "DTLB misses": 17888,
+    "DTLB accesses": 38223408,
+    "L1I cache accesses": 30063404,
+    "L1I cache misses": 272797,
+    "L1D cache misses": 468341,
+    "L1D cache accesses": 31519623,
+    "LL cache misses": 538689,
+    "LL cache accesses": 552789,
+    "L2D TLB accesses": 192995,
+    "L2D TLB misses": 23339,
+    "L2D cache misses": 300578,
+    "L2D cache accesses": 1764035,
+    "instructions per cycle": 1.344996515634638,
+    "branch miss rate": 0.016843728451145536,
+    "ITLB miss rate": 0.0002459414277933028,
+    "DTLB miss rate": 0.00046798548156668814,
+    "L2D TLB miss rate": 0.12093059405684085,
+    "L1I cache miss rate": 0.009074055619250568,
+    "L1D cache miss rate": 0.01485871198395996,
+    "L2D cache miss rate": 0.17039231081015965,
+    "LL cache miss rate": 0.9744929801425137,
+    "size": 581533225
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      51.04,
+      38.64,
+      22.84,
+      22.24,
+      21.88,
+      21.88,
+      21.6,
+      21.4,
+      21.24,
+      21.28
+    ],
+    "matrix": "ga2010",
+    "shape": [
+      291086,
+      291086
+    ],
+    "nnz": 1418056,
+    "% density": 1.6735964475229304e-05,
+    "time_s": 15.249999523162842,
+    "power": [
+      88.88,
+      89.52,
+      78.6,
+      64.88,
+      52.64,
+      52.64,
+      54.76,
+      60.16,
+      71.44,
+      86.84,
+      90.72,
+      89.6,
+      90.56,
+      90.36,
+      91.68,
+      91.84,
+      93.4,
+      93.4,
+      92.72
+    ],
+    "power_after": [
+      21.68,
+      21.4,
+      21.28,
+      21.04,
+      21.04,
+      20.96,
+      20.92,
+      20.76,
+      20.8,
+      20.96
+    ],
+    "task clock (msec)": 72.45,
+    "page faults": 3289,
+    "cycles": 24836161,
+    "instructions": 74134706,
+    "branch mispredictions": 325643,
+    "branches": 19697746,
+    "ITLB accesses": 27767290,
+    "ITLB misses": 5832,
+    "DTLB misses": 18134,
+    "DTLB accesses": 37063060,
+    "L1I cache accesses": 32135376,
+    "L1I cache misses": 302429,
+    "L1D cache misses": 484427,
+    "L1D cache accesses": 33639686,
+    "LL cache misses": 548380,
+    "LL cache accesses": 561312,
+    "L2D TLB accesses": 186006,
+    "L2D TLB misses": 25022,
+    "L2D cache misses": 304539,
+    "L2D cache accesses": 1750107,
+    "instructions per cycle": 2.9849502908279586,
+    "branch miss rate": 0.01653199305138771,
+    "ITLB miss rate": 0.00021003129941740803,
+    "DTLB miss rate": 0.0004892742261432272,
+    "L2D TLB miss rate": 0.13452254228358226,
+    "L1I cache miss rate": 0.009411092622659838,
+    "L1D cache miss rate": 0.014400461407398393,
+    "L2D cache miss rate": 0.17401164614506429,
+    "LL cache miss rate": 0.976961119662505,
+    "size": 84731059396
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      22.04,
+      21.32,
+      21.32,
+      21.32,
+      21.12,
+      21.12,
+      21.0,
+      20.68,
+      20.72,
+      20.56
+    ],
+    "matrix": "mac_econ_fwd500",
+    "shape": [
+      206500,
+      206500
+    ],
+    "nnz": 1273389,
+    "% density": 2.9862143765866013e-05,
+    "time_s": 15.046087741851807,
+    "power": [
+      91.88,
+      91.12,
+      83.92,
+      72.88,
+      57.76,
+      51.24,
+      53.12,
+      62.84,
+      78.32,
+      91.64,
+      95.8,
+      95.8,
+      94.08,
+      92.48,
+      91.6,
+      89.88,
+      87.36,
+      87.84,
+      87.32
+    ],
+    "power_after": [
+      20.92,
+      21.04,
+      21.12,
+      20.92,
+      20.92,
+      20.88,
+      20.88,
+      20.92,
+      21.04,
+      20.96
+    ],
+    "task clock (msec)": 62.46,
+    "page faults": 3243,
+    "cycles": 57150420,
+    "instructions": 94155455,
+    "branch mispredictions": 320781,
+    "branches": 19491698,
+    "ITLB accesses": 27433101,
+    "ITLB misses": 7382,
+    "DTLB misses": 19213,
+    "DTLB accesses": 37123052,
+    "L1I cache accesses": 32027284,
+    "L1I cache misses": 290368,
+    "L1D cache misses": 471338,
+    "L1D cache accesses": 33366668,
+    "LL cache misses": 571063,
+    "LL cache accesses": 583554,
+    "L2D TLB accesses": 196434,
+    "L2D TLB misses": 25171,
+    "L2D cache misses": 329198,
+    "L2D cache accesses": 1814040,
+    "instructions per cycle": 1.6475024155553013,
+    "branch miss rate": 0.016457314288370363,
+    "ITLB miss rate": 0.0002690909788142434,
+    "DTLB miss rate": 0.0005175490420345827,
+    "L2D TLB miss rate": 0.1281397314110592,
+    "L1I cache miss rate": 0.009066269871650684,
+    "L1D cache miss rate": 0.014126013421537926,
+    "L2D cache miss rate": 0.1814722938854711,
+    "LL cache miss rate": 0.9785949543658342,
+    "size": 42642250000
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      94.16,
+      91.68,
+      78.92,
+      60.88,
+      46.72,
+      28.36,
+      22.08,
+      21.64,
+      21.64,
+      21.64
+    ],
+    "matrix": "mc2depi",
+    "shape": [
+      525825,
+      525825
+    ],
+    "nnz": 2100225,
+    "% density": 7.595972132902821e-06,
+    "time_s": 11.03979206085205,
+    "power": [
+      95.44,
+      94.0,
+      88.76,
+      72.12,
+      59.48,
+      51.92,
+      53.88,
+      68.6,
+      83.2,
+      97.76,
+      98.4,
+      97.12,
+      97.12,
+      95.28,
+      94.12
+    ],
+    "power_after": [
+      21.48,
+      21.44,
+      21.28,
+      21.24,
+      21.16,
+      21.08,
+      21.24,
+      21.24,
+      21.24,
+      21.16
+    ],
+    "task clock (msec)": 56.14,
+    "page faults": 3289,
+    "cycles": 47515158,
+    "instructions": 72388154,
+    "branch mispredictions": 327042,
+    "branches": 19309026,
+    "ITLB accesses": 26093030,
+    "ITLB misses": 6189,
+    "DTLB misses": 17253,
+    "DTLB accesses": 35168741,
+    "L1I cache accesses": 30539322,
+    "L1I cache misses": 285404,
+    "L1D cache misses": 465747,
+    "L1D cache accesses": 31932803,
+    "LL cache misses": 530261,
+    "LL cache accesses": 551030,
+    "L2D TLB accesses": 183570,
+    "L2D TLB misses": 23883,
+    "L2D cache misses": 297006,
+    "L2D cache accesses": 1721848,
+    "instructions per cycle": 1.5234749719236964,
+    "branch miss rate": 0.01693726032581861,
+    "ITLB miss rate": 0.0002371897782664566,
+    "DTLB miss rate": 0.0004905776979619486,
+    "L2D TLB miss rate": 0.13010295799967314,
+    "L1I cache miss rate": 0.009345459601231487,
+    "L1D cache miss rate": 0.014585221347465175,
+    "L2D cache miss rate": 0.1724925777420539,
+    "LL cache miss rate": 0.9623087672177558,
+    "size": 276491930625
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      30.72,
+      30.6,
+      28.68,
+      26.48,
+      22.44,
+      21.4,
+      21.28,
+      21.08,
+      21.32,
+      21.6
+    ],
+    "matrix": "p2p-Gnutella24",
+    "shape": [
+      26518,
+      26518
+    ],
+    "nnz": 65369,
+    "% density": 9.295875717624285e-05,
+    "time_s": 1.718301773071289,
+    "power": [
+      31.52,
+      32.48,
+      33.64,
+      33.88,
+      33.44,
+      31.52
+    ],
+    "power_after": [
+      20.96,
+      20.84,
+      20.92,
+      20.8,
+      20.76,
+      20.76,
+      20.76,
+      20.68,
+      20.72,
+      20.92
+    ],
+    "task clock (msec)": 67.08,
+    "page faults": 3303,
+    "cycles": 61261862,
+    "instructions": 83757591,
+    "branch mispredictions": 329248,
+    "branches": 19953212,
+    "ITLB accesses": 27084694,
+    "ITLB misses": 7107,
+    "DTLB misses": 17529,
+    "DTLB accesses": 36684333,
+    "L1I cache accesses": 32158234,
+    "L1I cache misses": 286484,
+    "L1D cache misses": 474161,
+    "L1D cache accesses": 33730073,
+    "LL cache misses": 550064,
+    "LL cache accesses": 565245,
+    "L2D TLB accesses": 191046,
+    "L2D TLB misses": 23775,
+    "L2D cache misses": 307419,
+    "L2D cache accesses": 1772169,
+    "instructions per cycle": 1.3672060930828385,
+    "branch miss rate": 0.016501002445120115,
+    "ITLB miss rate": 0.0002623991247602797,
+    "DTLB miss rate": 0.0004778334118818516,
+    "L2D TLB miss rate": 0.12444646838981188,
+    "L1I cache miss rate": 0.008908573773049851,
+    "L1D cache miss rate": 0.014057514788064645,
+    "L2D cache miss rate": 0.1734704760099065,
+    "LL cache miss rate": 0.973142619572044,
+    "size": 703204324
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      86.48,
+      72.16,
+      59.36,
+      41.84,
+      28.44,
+      22.96,
+      22.92,
+      22.92,
+      23.04,
+      23.24
+    ],
+    "matrix": "p2p-Gnutella25",
+    "shape": [
+      22687,
+      22687
+    ],
+    "nnz": 54705,
+    "% density": 0.00010628522108964806,
+    "time_s": 1.431199073791504,
+    "power": [
+      35.16,
+      36.2,
+      36.72,
+      37.52,
+      37.52
+    ],
+    "power_after": [
+      21.32,
+      21.2,
+      21.2,
+      21.28,
+      21.52,
+      21.44,
+      21.92,
+      21.68,
+      21.6,
+      21.36
+    ],
+    "task clock (msec)": 59.85,
+    "page faults": 3318,
+    "cycles": 76505130,
+    "instructions": 72343215,
+    "branch mispredictions": 322338,
+    "branches": 19784096,
+    "ITLB accesses": 27270404,
+    "ITLB misses": 6607,
+    "DTLB misses": 17981,
+    "DTLB accesses": 36751047,
+    "L1I cache accesses": 30620441,
+    "L1I cache misses": 302139,
+    "L1D cache misses": 471011,
+    "L1D cache accesses": 32141810,
+    "LL cache misses": 531907,
+    "LL cache accesses": 545159,
+    "L2D TLB accesses": 188244,
+    "L2D TLB misses": 23034,
+    "L2D cache misses": 293848,
+    "L2D cache accesses": 1757551,
+    "instructions per cycle": 0.945599530384433,
+    "branch miss rate": 0.016292783860329025,
+    "ITLB miss rate": 0.00024227730546272803,
+    "DTLB miss rate": 0.0004892649725054092,
+    "L2D TLB miss rate": 0.12236246573595971,
+    "L1I cache miss rate": 0.009867232153841285,
+    "L1D cache miss rate": 0.014654152955294054,
+    "L2D cache miss rate": 0.1671917344077071,
+    "LL cache miss rate": 0.9756914955086498,
+    "size": 514699969
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      77.2,
+      64.12,
+      64.12,
+      48.92,
+      36.2,
+      21.72,
+      21.88,
+      22.36,
+      22.36,
+      22.44
+    ],
+    "matrix": "vt2010",
+    "shape": [
+      32580,
+      32580
+    ],
+    "nnz": 155598,
+    "% density": 0.00014658915806621921,
+    "time_s": 3.5892834663391113,
+    "power": [
+      33.44,
+      30.68,
+      31.08,
+      26.96,
+      26.88,
+      32.48,
+      32.24
+    ],
+    "power_after": [
+      21.24,
+      21.24,
+      21.36,
+      21.36,
+      21.2,
+      21.04,
+      20.84,
+      20.72,
+      20.72,
+      20.56
+    ],
+    "task clock (msec)": 55.26,
+    "page faults": 3297,
+    "cycles": 49276491,
+    "instructions": 64763517,
+    "branch mispredictions": 340611,
+    "branches": 20355849,
+    "ITLB accesses": 27946393,
+    "ITLB misses": 6805,
+    "DTLB misses": 17877,
+    "DTLB accesses": 38226912,
+    "L1I cache accesses": 31946141,
+    "L1I cache misses": 295259,
+    "L1D cache misses": 468136,
+    "L1D cache accesses": 33395666,
+    "LL cache misses": 527109,
+    "LL cache accesses": 540409,
+    "L2D TLB accesses": 192519,
+    "L2D TLB misses": 24204,
+    "L2D cache misses": 290933,
+    "L2D cache accesses": 1743452,
+    "instructions per cycle": 1.3142883286880147,
+    "branch miss rate": 0.016732831924622747,
+    "ITLB miss rate": 0.00024350190738389746,
+    "DTLB miss rate": 0.0004676548291423592,
+    "L2D TLB miss rate": 0.1257226559456469,
+    "L1I cache miss rate": 0.009242399574959616,
+    "L1D cache miss rate": 0.014017866869311724,
+    "L2D cache miss rate": 0.16687181522634406,
+    "LL cache miss rate": 0.9753890109158063,
+    "size": 1061456400
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      93.52,
+      87.76,
+      71.6,
+      58.32,
+      39.6,
+      26.24,
+      26.24,
+      22.16,
+      22.24,
+      22.24
+    ],
+    "matrix": "ut2010",
+    "shape": [
+      115406,
+      115406
+    ],
+    "nnz": 572066,
+    "% density": 4.295259032005559e-05,
+    "time_s": 8.478580713272095,
+    "power": [
+      89.68,
+      88.92,
+      80.84,
+      68.96,
+      56.64,
+      54.52,
+      55.88,
+      70.44,
+      85.36,
+      85.36,
+      98.2,
+      96.52
+    ],
+    "power_after": [
+      21.24,
+      21.32,
+      21.16,
+      21.44,
+      21.68,
+      21.76,
+      21.72,
+      22.0,
+      21.72,
+      21.72
+    ],
+    "task clock (msec)": 53.84,
+    "page faults": 3291,
+    "cycles": 66389970,
+    "instructions": 74935543,
+    "branch mispredictions": 330515,
+    "branches": 19475058,
+    "ITLB accesses": 26125490,
+    "ITLB misses": 6431,
+    "DTLB misses": 13728,
+    "DTLB accesses": 35274185,
+    "L1I cache accesses": 30428652,
+    "L1I cache misses": 288897,
+    "L1D cache misses": 475615,
+    "L1D cache accesses": 31855716,
+    "LL cache misses": 553829,
+    "LL cache accesses": 574192,
+    "L2D TLB accesses": 181148,
+    "L2D TLB misses": 23202,
+    "L2D cache misses": 307806,
+    "L2D cache accesses": 1767037,
+    "instructions per cycle": 1.1287178319255153,
+    "branch miss rate": 0.016971194642911976,
+    "ITLB miss rate": 0.00024615806248992844,
+    "DTLB miss rate": 0.0003891797925309968,
+    "L2D TLB miss rate": 0.12808311435952924,
+    "L1I cache miss rate": 0.009494242465949527,
+    "L1D cache miss rate": 0.014930287550278261,
+    "L2D cache miss rate": 0.17419329646181717,
+    "LL cache miss rate": 0.9645362526820297,
+    "size": 13318544836
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      20.72,
+      20.8,
+      20.96,
+      21.08,
+      21.4,
+      21.48,
+      21.48,
+      21.36,
+      21.08,
+      21.04
+    ],
+    "matrix": "fl2010",
+    "shape": [
+      484481,
+      484481
+    ],
+    "nnz": 2346294,
+    "% density": 9.99606174861054e-06,
+    "time_s": 14.43001127243042,
+    "power": [
+      93.04,
+      93.04,
+      89.16,
+      77.68,
+      62.92,
+      55.12,
+      53.84,
+      64.72,
+      77.04,
+      89.56,
+      94.4,
+      94.76,
+      93.52,
+      93.52,
+      96.04,
+      97.12,
+      96.44,
+      93.88,
+      93.72
+    ],
+    "power_after": [
+      21.08,
+      21.28,
+      21.28,
+      21.36,
+      21.08,
+      21.24,
+      21.08,
+      20.8,
+      21.04,
+      20.88
+    ],
+    "task clock (msec)": 61.6,
+    "page faults": 3276,
+    "cycles": 41408849,
+    "instructions": 49118917,
+    "branch mispredictions": 331330,
+    "branches": 19331189,
+    "ITLB accesses": 27367982,
+    "ITLB misses": 6160,
+    "DTLB misses": 17157,
+    "DTLB accesses": 36828216,
+    "L1I cache accesses": 30147304,
+    "L1I cache misses": 280082,
+    "L1D cache misses": 454022,
+    "L1D cache accesses": 31595140,
+    "LL cache misses": 536056,
+    "LL cache accesses": 550006,
+    "L2D TLB accesses": 185998,
+    "L2D TLB misses": 23735,
+    "L2D cache misses": 296648,
+    "L2D cache accesses": 1723525,
+    "instructions per cycle": 1.1861937287848787,
+    "branch miss rate": 0.017139659645353425,
+    "ITLB miss rate": 0.00022508053388810325,
+    "DTLB miss rate": 0.00046586562867992305,
+    "L2D TLB miss rate": 0.12760889902041958,
+    "L1I cache miss rate": 0.009290449321770198,
+    "L1D cache miss rate": 0.014369994878959232,
+    "L2D cache miss rate": 0.172117027603313,
+    "LL cache miss rate": 0.97463664032756,
+    "size": 234721839361
+  },
+  {
+    "architecture": "altra",
+    "iterations": 1000,
+    "baseline_time_s": 10,
+    "baseline_delay_s": 30,
+    "power_before": [
+      37.56,
+      23.12,
+      22.32,
+      22.28,
+      22.28,
+      21.96,
+      21.76,
+      21.72,
+      21.88,
+      21.84
+    ],
+    "matrix": "tn2010",
+    "shape": [
+      240116,
+      240116
+    ],
+    "nnz": 1193966,
+    "% density": 2.070855328296721e-05,
+    "time_s": 16.282614707946777,
+    "power": [
+      85.48,
+      85.84,
+      79.28,
+      70.16,
+      55.52,
+      49.48,
+      49.48,
+      60.48,
+      76.32,
+      88.88,
+      91.0,
+      91.0,
+      90.68,
+      88.32,
+      86.92,
+      86.4,
+      88.08,
+      86.8,
+      87.32,
+      87.8
+    ],
+    "power_after": [
+      21.68,
+      21.48,
+      21.44,
+      21.36,
+      21.52,
+      21.4,
+      21.4,
+      21.32,
+      21.2,
+      21.04
+    ],
+    "task clock (msec)": 68.11,
+    "page faults": 3486,
+    "cycles": 70427921,
+    "instructions": 85638293,
+    "branch mispredictions": 333780,
+    "branches": 19402540,
+    "ITLB accesses": 26935483,
+    "ITLB misses": 5639,
+    "DTLB misses": 16688,
+    "DTLB accesses": 36421540,
+    "L1I cache accesses": 33029213,
+    "L1I cache misses": 302558,
+    "L1D cache misses": 481598,
+    "L1D cache accesses": 34668833,
+    "LL cache misses": 551659,
+    "LL cache accesses": 564579,
+    "L2D TLB accesses": 188346,
+    "L2D TLB misses": 24479,
+    "L2D cache misses": 311796,
+    "L2D cache accesses": 1767924,
+    "instructions per cycle": 1.215970765344614,
+    "branch miss rate": 0.017202902300420462,
+    "ITLB miss rate": 0.0002093521025778524,
+    "DTLB miss rate": 0.00045819040051573877,
+    "L2D TLB miss rate": 0.12996824992301403,
+    "L1I cache miss rate": 0.00916031514284037,
+    "L1D cache miss rate": 0.013891381922200843,
+    "L2D cache miss rate": 0.17636278482559206,
+    "LL cache miss rate": 0.9771156915152707,
+    "size": 57655693456
+  }
+]
\ No newline at end of file