[ { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell26", "maxwell size": 26, "matrix columns": 56862, "task clock (msec)": 31.67, "page faults": 2757, "cycles": 34506129, "instructions": 75341056, "branch mispredictions": 315890, "branches": 16795763, "ITLB accesses": 22839688, "ITLB misses": 5094, "DTLB misses": 12448, "DTLB accesses": 30552656, "L1I cache accesses": 26241679, "L1I cache misses": 230488, "L1D cache misses": 376311, "L1D cache accesses": 27346779, "LL cache misses": 470446, "LL cache accesses": 497357, "L2D TLB accesses": 133794, "L2D TLB misses": 17138, "L2D cache misses": 260141, "L2D cache accesses": 1449409, "\u0394 watt": 7.638666666666673, "branch miss rate": 0.018807719542124998, "ITLB miss rate": 0.00022303281901223869, "DTLB miss rate": 0.0004074277535805725, "L1I cache miss rate": 0.008783279454031886, "L1D cache miss rate": 0.01376070651684427, "L2D cache miss rate": 0.17948074008095713, "LL cache miss rate": 0.9458919850328839 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 31.99, "page faults": 2748, "cycles": 30819840, "instructions": 74713950, "branch mispredictions": 314555, "branches": 17082499, "ITLB accesses": 22662021, "ITLB misses": 5013, "DTLB misses": 12452, "DTLB accesses": 30478553, "L1I cache accesses": 26662876, "L1I cache misses": 236659, "L1D cache misses": 385640, "L1D cache accesses": 27887366, "LL cache misses": 475900, "LL cache accesses": 504259, "L2D TLB accesses": 134409, "L2D TLB misses": 17441, "L2D cache misses": 263745, "L2D cache accesses": 1481533, "\u0394 watt": 3.9360000000000035, "branch miss rate": 0.018413874925442702, "ITLB miss rate": 0.00022120710240273805, "DTLB miss rate": 0.00040854957910895574, "L1I cache miss rate": 0.008875974219735336, "L1D cache miss rate": 0.01382848419603343, "L2D cache miss rate": 0.1780216842959286, "LL cache miss rate": 0.9437610434320458 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell36", "maxwell size": 36, "matrix columns": 147852, "task clock (msec)": 35.04, "page faults": 2789, "cycles": 36247748, "instructions": 75696892, "branch mispredictions": 317778, "branches": 16939023, "ITLB accesses": 22586635, "ITLB misses": 5111, "DTLB misses": 12387, "DTLB accesses": 30378289, "L1I cache accesses": 26656102, "L1I cache misses": 231037, "L1D cache misses": 379530, "L1D cache accesses": 28042717, "LL cache misses": 467202, "LL cache accesses": 500467, "L2D TLB accesses": 137989, "L2D TLB misses": 18528, "L2D cache misses": 262804, "L2D cache accesses": 1482821, "\u0394 watt": 15.126666666666672, "branch miss rate": 0.01876011385072209, "ITLB miss rate": 0.00022628426058153418, "DTLB miss rate": 0.0004077583171323441, "L1I cache miss rate": 0.008667321276006522, "L1D cache miss rate": 0.013533995297245983, "L2D cache miss rate": 0.17723245084875383, "LL cache miss rate": 0.9335320810363121 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 27.15, "page faults": 2747, "cycles": 45356846, "instructions": 77730625, "branches": 16888960, "branch mispredictions": 290099, "ITLB accesses": 7996, "ITLB misses": 14530, "DTLB accesses": 17640131, "DTLB misses": 14505, "L1D cache accesses": 17593501, "L1D cache misses": 574293, "LL cache accesses": 62141, "LL cache misses": 10948, "branch miss rate": 0.017176842150138316, "ITLB miss rate": 1.8171585792896447, "DTLB miss rate": 0.0008222728051169234, "L1I cache miss rate": null, "L1D cache miss rate": 0.03264233764502017, "L2D cache miss rate": null, "LL cache miss rate": 0.17617997779243977 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 31.09, "page faults": 3226, "cycles": 50299542, "instructions": 77878301, "branches": 16919929, "branch mispredictions": 292094, "ITLB accesses": 7694, "ITLB misses": 13886, "DTLB accesses": 17764513, "DTLB misses": 12428, "L1D cache accesses": 17864775, "L1D cache misses": 574110, "LL cache accesses": 65570, "LL cache misses": 25239, "branch miss rate": 0.01726331121129409, "ITLB miss rate": 1.8047829477514947, "DTLB miss rate": 0.0006995969999290158, "L1I cache miss rate": null, "L1D cache miss rate": 0.03213642489200116, "L2D cache miss rate": null, "LL cache miss rate": 0.38491688272075647 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 34.72, "page faults": 2791, "cycles": 37907762, "instructions": 75121705, "branch mispredictions": 313698, "branches": 16778291, "ITLB accesses": 22495586, "ITLB misses": 4976, "DTLB misses": 12077, "DTLB accesses": 30380854, "L1I cache accesses": 26482288, "L1I cache misses": 235168, "L1D cache misses": 385004, "L1D cache accesses": 27728465, "LL cache misses": 468613, "LL cache accesses": 492063, "L2D TLB accesses": 134110, "L2D TLB misses": 17486, "L2D cache misses": 255725, "L2D cache accesses": 1452539, "\u0394 watt": 3.1706666666666656, "branch miss rate": 0.0186966598683978, "ITLB miss rate": 0.0002211989498739886, "DTLB miss rate": 0.00039752009604469976, "L1I cache miss rate": 0.008880199475211507, "L1D cache miss rate": 0.01388479311783036, "L2D cache miss rate": 0.17605379270367266, "LL cache miss rate": 0.9523435007305975 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 31.98, "page faults": 2783, "cycles": 30882808, "instructions": 74791258, "branch mispredictions": 311433, "branches": 16883258, "ITLB accesses": 22674676, "ITLB misses": 5239, "DTLB misses": 12341, "DTLB accesses": 30377113, "L1I cache accesses": 26540749, "L1I cache misses": 238727, "L1D cache misses": 377012, "L1D cache accesses": 27809507, "LL cache misses": 468899, "LL cache accesses": 496246, "L2D TLB accesses": 134879, "L2D TLB misses": 17575, "L2D cache misses": 257854, "L2D cache accesses": 1458582, "\u0394 watt": 5.262666666666668, "branch miss rate": 0.018446261971474937, "ITLB miss rate": 0.00023105071049306283, "DTLB miss rate": 0.00040625980487349144, "L1I cache miss rate": 0.008994734850926776, "L1D cache miss rate": 0.013556946550688584, "L2D cache miss rate": 0.1767840272264432, "LL cache miss rate": 0.9448922510206631 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 36.03, "page faults": 2754, "cycles": 31415325, "instructions": 73820867, "branch mispredictions": 312352, "branches": 16726998, "ITLB accesses": 22571063, "ITLB misses": 5115, "DTLB misses": 14900, "DTLB accesses": 30351769, "L1I cache accesses": 26977665, "L1I cache misses": 229090, "L1D cache misses": 367879, "L1D cache accesses": 28461927, "LL cache misses": 471301, "LL cache accesses": 499109, "L2D TLB accesses": 139843, "L2D TLB misses": 17816, "L2D cache misses": 262194, "L2D cache accesses": 1474249, "\u0394 watt": 3.3026666666666706, "branch miss rate": 0.018673524083640113, "ITLB miss rate": 0.00022661759439508898, "DTLB miss rate": 0.0004909104309537938, "L1I cache miss rate": 0.008491839453117978, "L1D cache miss rate": 0.012925301930540402, "L2D cache miss rate": 0.17784919643832214, "LL cache miss rate": 0.9442847153627765 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 36.85, "page faults": 2771, "cycles": 31621903, "instructions": 74382715, "branch mispredictions": 314723, "branches": 16785485, "ITLB accesses": 22955256, "ITLB misses": 5739, "DTLB misses": 12741, "DTLB accesses": 30795163, "L1I cache accesses": 26537679, "L1I cache misses": 236820, "L1D cache misses": 383053, "L1D cache accesses": 27799952, "LL cache misses": 467805, "LL cache accesses": 492372, "L2D TLB accesses": 134647, "L2D TLB misses": 18367, "L2D cache misses": 255210, "L2D cache accesses": 1477471, "\u0394 watt": 2.5333333333333314, "branch miss rate": 0.0187497114322285, "ITLB miss rate": 0.00025000810271948176, "DTLB miss rate": 0.0004137338061824839, "L1I cache miss rate": 0.008923915313015882, "L1D cache miss rate": 0.013778908683007797, "L2D cache miss rate": 0.17273435485366548, "LL cache miss rate": 0.9501047988106553 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 30.97, "page faults": 3251, "cycles": 49455687, "instructions": 78584469, "branches": 17039294, "branch mispredictions": 294966, "ITLB accesses": 8375, "ITLB misses": 14366, "DTLB accesses": 17909445, "DTLB misses": 14174, "L1D cache accesses": 17933423, "L1D cache misses": 585835, "LL cache accesses": 73948, "LL cache misses": 24797, "branch miss rate": 0.017310928492694593, "ITLB miss rate": 1.7153432835820897, "DTLB miss rate": 0.0007914259766285332, "L1I cache miss rate": null, "L1D cache miss rate": 0.0326672158460769, "L2D cache miss rate": null, "LL cache miss rate": 0.33533023205495754 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 30.87, "page faults": 2776, "cycles": 31027198, "instructions": 76269864, "branch mispredictions": 316045, "branches": 16843661, "ITLB accesses": 22397832, "ITLB misses": 5242, "DTLB misses": 12258, "DTLB accesses": 29979792, "L1I cache accesses": 26500659, "L1I cache misses": 242032, "L1D cache misses": 394893, "L1D cache accesses": 27722935, "LL cache misses": 475227, "LL cache accesses": 503677, "L2D TLB accesses": 135439, "L2D TLB misses": 18040, "L2D cache misses": 263775, "L2D cache accesses": 1471248, "\u0394 watt": 3.1733333333333285, "branch miss rate": 0.018763438660989437, "ITLB miss rate": 0.0002340405089206848, "DTLB miss rate": 0.0004088754184818894, "L1I cache miss rate": 0.009133055898723123, "L1D cache miss rate": 0.014244271034073412, "L2D cache miss rate": 0.17928656487553424, "LL cache miss rate": 0.9435153878378405 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell50", "maxwell size": 50, "matrix columns": 390150, "task clock (msec)": 34.95, "page faults": 2763, "cycles": 39116016, "instructions": 74243596, "branch mispredictions": 312342, "branches": 16630548, "ITLB accesses": 22877751, "ITLB misses": 5702, "DTLB misses": 15680, "DTLB accesses": 30809285, "L1I cache accesses": 26242223, "L1I cache misses": 238048, "L1D cache misses": 386115, "L1D cache accesses": 27462684, "LL cache misses": 476534, "LL cache accesses": 497710, "L2D TLB accesses": 138762, "L2D TLB misses": 18334, "L2D cache misses": 258881, "L2D cache accesses": 1470082, "\u0394 watt": 19.074666666666662, "branch miss rate": 0.01878122116000026, "ITLB miss rate": 0.0002492377856547175, "DTLB miss rate": 0.0005089374842681354, "L1I cache miss rate": 0.00907118272716454, "L1D cache miss rate": 0.014059623596877858, "L2D cache miss rate": 0.17609970056092109, "LL cache miss rate": 0.9574531353599486 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 27.37, "page faults": 2759, "cycles": 45348714, "instructions": 78309411, "branches": 17004157, "branch mispredictions": 290236, "ITLB accesses": 7105, "ITLB misses": 14499, "DTLB accesses": 17662985, "DTLB misses": 12679, "L1D cache accesses": 17593928, "L1D cache misses": 590492, "LL cache accesses": 65802, "LL cache misses": 11589, "branch miss rate": 0.017068532124232916, "ITLB miss rate": 2.0406755805770582, "DTLB miss rate": 0.0007178288381040917, "L1I cache miss rate": null, "L1D cache miss rate": 0.03356226079815718, "L2D cache miss rate": null, "LL cache miss rate": 0.17611926689158383 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 28.84, "page faults": 3251, "cycles": 46945863, "instructions": 78778600, "branches": 17089248, "branch mispredictions": 295353, "ITLB accesses": 9379, "ITLB misses": 15619, "DTLB accesses": 18062818, "DTLB misses": 14970, "L1D cache accesses": 17623645, "L1D cache misses": 587213, "LL cache accesses": 66288, "LL cache misses": 21398, "branch miss rate": 0.017282972311010992, "ITLB miss rate": 1.6653161317837724, "DTLB miss rate": 0.0008287743363189509, "L1I cache miss rate": null, "L1D cache miss rate": 0.03331961123819732, "L2D cache miss rate": null, "LL cache miss rate": 0.3228035240164132 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell24", "maxwell size": 24, "matrix columns": 45000, "task clock (msec)": 36.01, "page faults": 2758, "cycles": 39830909, "instructions": 74176381, "branch mispredictions": 317516, "branches": 16989939, "ITLB accesses": 22906292, "ITLB misses": 5412, "DTLB misses": 12307, "DTLB accesses": 30851528, "L1I cache accesses": 26290542, "L1I cache misses": 229175, "L1D cache misses": 379049, "L1D cache accesses": 27496626, "LL cache misses": 462574, "LL cache accesses": 487815, "L2D TLB accesses": 136529, "L2D TLB misses": 17906, "L2D cache misses": 252703, "L2D cache accesses": 1456088, "\u0394 watt": 8.513333333333332, "branch miss rate": 0.018688472042189205, "ITLB miss rate": 0.00023626696106030605, "DTLB miss rate": 0.0003989105499085815, "L1I cache miss rate": 0.008717013137271952, "L1D cache miss rate": 0.01378529132992535, "L2D cache miss rate": 0.17354926350605182, "LL cache miss rate": 0.9482570236667589 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell22", "maxwell size": 22, "matrix columns": 34914, "task clock (msec)": 37.47, "page faults": 2822, "cycles": 25704354, "instructions": 76290104, "branch mispredictions": 316665, "branches": 16856425, "ITLB accesses": 22772192, "ITLB misses": 5013, "DTLB misses": 12272, "DTLB accesses": 30469531, "L1I cache accesses": 26519195, "L1I cache misses": 236208, "L1D cache misses": 380374, "L1D cache accesses": 27752114, "LL cache misses": 474912, "LL cache accesses": 494530, "L2D TLB accesses": 138674, "L2D TLB misses": 17217, "L2D cache misses": 255454, "L2D cache accesses": 1459057, "\u0394 watt": 8.971999999999998, "branch miss rate": 0.018786011861945815, "ITLB miss rate": 0.0002201369108428385, "DTLB miss rate": 0.00040276300938140466, "L1I cache miss rate": 0.008907057699149616, "L1D cache miss rate": 0.013706127035944, "L2D cache miss rate": 0.1750815766621866, "LL cache miss rate": 0.9603300103128223 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 32.77, "page faults": 3269, "cycles": 51202082, "instructions": 79122810, "branches": 17153815, "branch mispredictions": 292733, "ITLB accesses": 8504, "ITLB misses": 15168, "DTLB accesses": 17800785, "DTLB misses": 14899, "L1D cache accesses": 17590854, "L1D cache misses": 583954, "LL cache accesses": 73737, "LL cache misses": 22820, "branch miss rate": 0.01706518345918969, "ITLB miss rate": 1.7836312323612418, "DTLB miss rate": 0.0008369855599064872, "L1I cache miss rate": null, "L1D cache miss rate": 0.033196455385281466, "L2D cache miss rate": null, "LL cache miss rate": 0.3094782809173142 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell32", "maxwell size": 32, "matrix columns": 104544, "task clock (msec)": 38.19, "page faults": 2764, "cycles": 28160037, "instructions": 75192743, "branch mispredictions": 316843, "branches": 16871544, "ITLB accesses": 22706983, "ITLB misses": 5437, "DTLB misses": 13067, "DTLB accesses": 30572002, "L1I cache accesses": 26441985, "L1I cache misses": 225564, "L1D cache misses": 376498, "L1D cache accesses": 27735954, "LL cache misses": 467890, "LL cache accesses": 492897, "L2D TLB accesses": 136869, "L2D TLB misses": 18307, "L2D cache misses": 257966, "L2D cache accesses": 1471080, "\u0394 watt": 11.0, "branch miss rate": 0.018779727569687755, "ITLB miss rate": 0.00023944176115338616, "DTLB miss rate": 0.00042741721657613396, "L1I cache miss rate": 0.008530524467054951, "L1D cache miss rate": 0.013574366326105099, "L2D cache miss rate": 0.17535824020447563, "LL cache miss rate": 0.9492652623164678 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 29.14, "page faults": 2775, "cycles": 47219016, "instructions": 79448945, "branches": 17214993, "branch mispredictions": 302959, "ITLB accesses": 7393, "ITLB misses": 14201, "DTLB accesses": 17643944, "DTLB misses": 13924, "L1D cache accesses": 17778098, "L1D cache misses": 587272, "LL cache accesses": 71448, "LL cache misses": 11360, "branch miss rate": 0.01759855493406242, "ITLB miss rate": 1.9208710942783713, "DTLB miss rate": 0.0007891659597196635, "L1I cache miss rate": null, "L1D cache miss rate": 0.03303345498489208, "L2D cache miss rate": null, "LL cache miss rate": 0.15899675288321577 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 29.05, "page faults": 3258, "cycles": 46083810, "instructions": 79091262, "branches": 17142768, "branch mispredictions": 298230, "ITLB accesses": 8268, "ITLB misses": 13948, "DTLB accesses": 17892377, "DTLB misses": 14417, "L1D cache accesses": 17736175, "L1D cache misses": 584957, "LL cache accesses": 71471, "LL cache misses": 11675, "branch miss rate": 0.01739684046357041, "ITLB miss rate": 1.686985970004838, "DTLB miss rate": 0.0008057621410503478, "L1I cache miss rate": null, "L1D cache miss rate": 0.03298101197129595, "L2D cache miss rate": null, "LL cache miss rate": 0.16335296833680793 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 32.22, "page faults": 2773, "cycles": 24403039, "instructions": 75230183, "branch mispredictions": 316164, "branches": 16836329, "ITLB accesses": 22779660, "ITLB misses": 5071, "DTLB misses": 12526, "DTLB accesses": 30516105, "L1I cache accesses": 26602529, "L1I cache misses": 240527, "L1D cache misses": 390271, "L1D cache accesses": 27837535, "LL cache misses": 474380, "LL cache accesses": 497098, "L2D TLB accesses": 135216, "L2D TLB misses": 17098, "L2D cache misses": 261466, "L2D cache accesses": 1451618, "\u0394 watt": 3.979999999999997, "branch miss rate": 0.018778677941016713, "ITLB miss rate": 0.0002226108730332235, "DTLB miss rate": 0.00041047178203116024, "L1I cache miss rate": 0.009041508797904139, "L1D cache miss rate": 0.01401959620347132, "L2D cache miss rate": 0.18012038979952025, "LL cache miss rate": 0.9542987499446789 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 29.43, "page faults": 3250, "cycles": 47251998, "instructions": 79570608, "branches": 17217585, "branch mispredictions": 297938, "ITLB accesses": 7313, "ITLB misses": 13770, "DTLB accesses": 17661992, "DTLB misses": 14273, "L1D cache accesses": 17655610, "L1D cache misses": 575913, "LL cache accesses": 66224, "LL cache misses": 11211, "branch miss rate": 0.017304285124772143, "ITLB miss rate": 1.882948174483796, "DTLB miss rate": 0.000808119491844408, "L1I cache miss rate": null, "L1D cache miss rate": 0.03261926379207515, "L2D cache miss rate": null, "LL cache miss rate": 0.16928907948779898 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell40", "maxwell size": 40, "matrix columns": 201720, "task clock (msec)": 36.17, "page faults": 2777, "cycles": 33198359, "instructions": 75365745, "branch mispredictions": 314158, "branches": 16970945, "ITLB accesses": 22549647, "ITLB misses": 4902, "DTLB misses": 12136, "DTLB accesses": 30309488, "L1I cache accesses": 26586747, "L1I cache misses": 232631, "L1D cache misses": 382824, "L1D cache accesses": 27869172, "LL cache misses": 444027, "LL cache accesses": 472773, "L2D TLB accesses": 160036, "L2D TLB misses": 21546, "L2D cache misses": 251471, "L2D cache accesses": 1491358, "\u0394 watt": 17.956, "branch miss rate": 0.01851152071967707, "ITLB miss rate": 0.00021738699501593084, "DTLB miss rate": 0.00040040267258886064, "L1I cache miss rate": 0.008749885798364125, "L1D cache miss rate": 0.013736468381622532, "L2D cache miss rate": 0.1686188024605762, "LL cache miss rate": 0.9391970353636946 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell32", "maxwell size": 32, "matrix columns": 104544, "task clock (msec)": 36.76, "page faults": 2775, "cycles": 34850201, "instructions": 75677644, "branch mispredictions": 311509, "branches": 16732191, "ITLB accesses": 22461744, "ITLB misses": 5685, "DTLB misses": 12876, "DTLB accesses": 30259413, "L1I cache accesses": 26404687, "L1I cache misses": 225017, "L1D cache misses": 376676, "L1D cache accesses": 27688364, "LL cache misses": 470244, "LL cache accesses": 497265, "L2D TLB accesses": 138358, "L2D TLB misses": 19781, "L2D cache misses": 257258, "L2D cache accesses": 1475249, "\u0394 watt": 10.506666666666668, "branch miss rate": 0.018617346646353727, "ITLB miss rate": 0.0002530969990575977, "DTLB miss rate": 0.0004255204818414686, "L1I cache miss rate": 0.008521858259482493, "L1D cache miss rate": 0.013604126267626358, "L2D cache miss rate": 0.17438276521455023, "LL cache miss rate": 0.945660764381165 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 34.98, "page faults": 2770, "cycles": 35843362, "instructions": 74725085, "branch mispredictions": 315028, "branches": 16768662, "ITLB accesses": 22665706, "ITLB misses": 5219, "DTLB misses": 12254, "DTLB accesses": 30493094, "L1I cache accesses": 26628016, "L1I cache misses": 240445, "L1D cache misses": 377989, "L1D cache accesses": 27940782, "LL cache misses": 470547, "LL cache accesses": 499243, "L2D TLB accesses": 137928, "L2D TLB misses": 17380, "L2D cache misses": 260705, "L2D cache accesses": 1463776, "\u0394 watt": 11.36266666666667, "branch miss rate": 0.018786710591459234, "ITLB miss rate": 0.000230259758950372, "DTLB miss rate": 0.00040186148378383644, "L1I cache miss rate": 0.009029775256256417, "L1D cache miss rate": 0.013528218358383814, "L2D cache miss rate": 0.17810443674441992, "LL cache miss rate": 0.9425209767588129 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 35.41, "page faults": 2765, "cycles": 37140362, "instructions": 73876599, "branch mispredictions": 316750, "branches": 16782719, "ITLB accesses": 22797676, "ITLB misses": 5406, "DTLB misses": 12331, "DTLB accesses": 30733042, "L1I cache accesses": 26630439, "L1I cache misses": 237304, "L1D cache misses": 387464, "L1D cache accesses": 27899970, "LL cache misses": 465815, "LL cache accesses": 485283, "L2D TLB accesses": 135965, "L2D TLB misses": 17774, "L2D cache misses": 248162, "L2D cache accesses": 1468216, "\u0394 watt": 2.949333333333332, "branch miss rate": 0.018873580615870408, "ITLB miss rate": 0.0002371294337194721, "DTLB miss rate": 0.0004012293999402988, "L1I cache miss rate": 0.008911005935726407, "L1D cache miss rate": 0.013887613499225985, "L2D cache miss rate": 0.1690228140818517, "LL cache miss rate": 0.9598832021727528 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell50", "maxwell size": 50, "matrix columns": 390150, "task clock (msec)": 35.49, "page faults": 2748, "cycles": 34782600, "instructions": 74053260, "branch mispredictions": 313370, "branches": 16823321, "ITLB accesses": 22512244, "ITLB misses": 5600, "DTLB misses": 12405, "DTLB accesses": 30301609, "L1I cache accesses": 26779507, "L1I cache misses": 227711, "L1D cache misses": 376129, "L1D cache accesses": 28040627, "LL cache misses": 459818, "LL cache accesses": 479002, "L2D TLB accesses": 134426, "L2D TLB misses": 16836, "L2D cache misses": 242825, "L2D cache accesses": 1441765, "\u0394 watt": 14.554666666666673, "branch miss rate": 0.018627118866720787, "ITLB miss rate": 0.00024875352274966457, "DTLB miss rate": 0.0004093842013471958, "L1I cache miss rate": 0.008503181182536334, "L1D cache miss rate": 0.013413715748938139, "L2D cache miss rate": 0.16842203826559807, "LL cache miss rate": 0.9599500628389861 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 26.61, "page faults": 2740, "cycles": 44146579, "instructions": 77589125, "branches": 16882608, "branch mispredictions": 287427, "ITLB accesses": 8158, "ITLB misses": 13803, "DTLB accesses": 17689973, "DTLB misses": 13768, "L1D cache accesses": 18106537, "L1D cache misses": 582639, "LL cache accesses": 68276, "LL cache misses": 10203, "branch miss rate": 0.01702503546845369, "ITLB miss rate": 1.6919588134346653, "DTLB miss rate": 0.0007782940087019918, "L1I cache miss rate": null, "L1D cache miss rate": 0.03217837844972785, "L2D cache miss rate": null, "LL cache miss rate": 0.14943757689378406 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell46", "maxwell size": 46, "matrix columns": 304842, "task clock (msec)": 37.23, "page faults": 2814, "cycles": 36640121, "instructions": 75770899, "branch mispredictions": 310974, "branches": 16838522, "ITLB accesses": 22880055, "ITLB misses": 4914, "DTLB misses": 11877, "DTLB accesses": 30814344, "L1I cache accesses": 26417580, "L1I cache misses": 232026, "L1D cache misses": 380204, "L1D cache accesses": 27687572, "LL cache misses": 462660, "LL cache accesses": 484240, "L2D TLB accesses": 136834, "L2D TLB misses": 17359, "L2D cache misses": 250884, "L2D cache accesses": 1453835, "\u0394 watt": 13.985333333333333, "branch miss rate": 0.018468010434645035, "ITLB miss rate": 0.00021477221099337393, "DTLB miss rate": 0.0003854373794230375, "L1I cache miss rate": 0.008783014946864929, "L1D cache miss rate": 0.013731937202727635, "L2D cache miss rate": 0.17256703821272704, "LL cache miss rate": 0.955435321328267 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell38", "maxwell size": 38, "matrix columns": 173394, "task clock (msec)": 35.51, "page faults": 2769, "cycles": 34057119, "instructions": 74858259, "branch mispredictions": 312992, "branches": 16734878, "ITLB accesses": 22407965, "ITLB misses": 4664, "DTLB misses": 11467, "DTLB accesses": 30143975, "L1I cache accesses": 26380461, "L1I cache misses": 224524, "L1D cache misses": 380936, "L1D cache accesses": 27654401, "LL cache misses": 464375, "LL cache accesses": 488020, "L2D TLB accesses": 132180, "L2D TLB misses": 18494, "L2D cache misses": 253615, "L2D cache accesses": 1460608, "\u0394 watt": 11.418666666666667, "branch miss rate": 0.018702974709466063, "ITLB miss rate": 0.0002081402751209224, "DTLB miss rate": 0.0003804076934113699, "L1I cache miss rate": 0.008510996073950337, "L1D cache miss rate": 0.013774878002239137, "L2D cache miss rate": 0.1736365951713259, "LL cache miss rate": 0.9515491168394737 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell50", "maxwell size": 50, "matrix columns": 390150, "task clock (msec)": 32.64, "page faults": 2756, "cycles": 35412935, "instructions": 74655974, "branch mispredictions": 316213, "branches": 16775798, "ITLB accesses": 22688159, "ITLB misses": 5553, "DTLB misses": 12575, "DTLB accesses": 30436074, "L1I cache accesses": 26563956, "L1I cache misses": 245142, "L1D cache misses": 385092, "L1D cache accesses": 27790301, "LL cache misses": 469441, "LL cache accesses": 501026, "L2D TLB accesses": 138495, "L2D TLB misses": 19115, "L2D cache misses": 262301, "L2D cache accesses": 1493319, "\u0394 watt": 18.674666666666667, "branch miss rate": 0.018849356674418706, "ITLB miss rate": 0.0002447532212728234, "DTLB miss rate": 0.00041316104041539656, "L1I cache miss rate": 0.00922836944918897, "L1D cache miss rate": 0.013857064736362517, "L2D cache miss rate": 0.17564967699466758, "LL cache miss rate": 0.9369593593945225 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 31.26, "page faults": 3259, "cycles": 50199983, "instructions": 79261227, "branches": 17172254, "branch mispredictions": 298417, "ITLB accesses": 9179, "ITLB misses": 15360, "DTLB accesses": 17844537, "DTLB misses": 15261, "L1D cache accesses": 17823138, "L1D cache misses": 578648, "LL cache accesses": 70731, "LL cache misses": 24360, "branch miss rate": 0.017377858491960343, "ITLB miss rate": 1.6733849003159385, "DTLB miss rate": 0.0008552197235490055, "L1I cache miss rate": null, "L1D cache miss rate": 0.03246611230861816, "L2D cache miss rate": null, "LL cache miss rate": 0.34440344403444034 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 34.07, "page faults": 2759, "cycles": 35815677, "instructions": 75698838, "branch mispredictions": 308569, "branches": 16734313, "ITLB accesses": 22865588, "ITLB misses": 4963, "DTLB misses": 12200, "DTLB accesses": 30667114, "L1I cache accesses": 26435684, "L1I cache misses": 231434, "L1D cache misses": 386049, "L1D cache accesses": 27683683, "LL cache misses": 472377, "LL cache accesses": 499919, "L2D TLB accesses": 134780, "L2D TLB misses": 17580, "L2D cache misses": 263006, "L2D cache accesses": 1483782, "\u0394 watt": 3.6693333333333342, "branch miss rate": 0.018439298942239217, "ITLB miss rate": 0.00021705105506143117, "DTLB miss rate": 0.000397820283969336, "L1I cache miss rate": 0.008754606084714888, "L1D cache miss rate": 0.013945001465303588, "L2D cache miss rate": 0.17725380143444253, "LL cache miss rate": 0.9449070749461412 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell34", "maxwell size": 34, "matrix columns": 124950, "task clock (msec)": 35.39, "page faults": 2757, "cycles": 35019558, "instructions": 73884050, "branch mispredictions": 311820, "branches": 17013235, "ITLB accesses": 22753628, "ITLB misses": 5573, "DTLB misses": 12737, "DTLB accesses": 30471484, "L1I cache accesses": 26688842, "L1I cache misses": 234773, "L1D cache misses": 379425, "L1D cache accesses": 27966418, "LL cache misses": 444727, "LL cache accesses": 464326, "L2D TLB accesses": 158917, "L2D TLB misses": 21453, "L2D cache misses": 244029, "L2D cache accesses": 1473015, "\u0394 watt": 12.477333333333334, "branch miss rate": 0.01832808398872995, "ITLB miss rate": 0.00024492797368402087, "DTLB miss rate": 0.0004179973643554741, "L1I cache miss rate": 0.00879667240714303, "L1D cache miss rate": 0.013567164733073789, "L2D cache miss rate": 0.165666337410006, "LL cache miss rate": 0.9577904317225397 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell42", "maxwell size": 42, "matrix columns": 232974, "task clock (msec)": 38.94, "page faults": 2771, "cycles": 38604757, "instructions": 77657485, "branch mispredictions": 311614, "branches": 16694225, "ITLB accesses": 22898357, "ITLB misses": 5552, "DTLB misses": 13048, "DTLB accesses": 30770993, "L1I cache accesses": 26383983, "L1I cache misses": 223528, "L1D cache misses": 375899, "L1D cache accesses": 27687659, "LL cache misses": 458067, "LL cache accesses": 477325, "L2D TLB accesses": 134565, "L2D TLB misses": 17564, "L2D cache misses": 245351, "L2D cache accesses": 1438299, "\u0394 watt": 12.877333333333336, "branch miss rate": 0.01866597580899982, "ITLB miss rate": 0.00024246281075974142, "DTLB miss rate": 0.0004240357144145462, "L1I cache miss rate": 0.008472109764473393, "L1D cache miss rate": 0.013576409619895998, "L2D cache miss rate": 0.17058414140592465, "LL cache miss rate": 0.9596543235740848 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell34", "maxwell size": 34, "matrix columns": 124950, "task clock (msec)": 31.69, "page faults": 2762, "cycles": 31887058, "instructions": 74429157, "branch mispredictions": 319093, "branches": 16928644, "ITLB accesses": 22662945, "ITLB misses": 5028, "DTLB misses": 12059, "DTLB accesses": 30464264, "L1I cache accesses": 26360446, "L1I cache misses": 225534, "L1D cache misses": 377754, "L1D cache accesses": 27615755, "LL cache misses": 454234, "LL cache accesses": 483749, "L2D TLB accesses": 155422, "L2D TLB misses": 22005, "L2D cache misses": 258239, "L2D cache accesses": 1497679, "\u0394 watt": 10.676000000000002, "branch miss rate": 0.01884929472201081, "ITLB miss rate": 0.0002218599568590931, "DTLB miss rate": 0.000395840844866628, "L1I cache miss rate": 0.00855577329761416, "L1D cache miss rate": 0.013678930740803574, "L2D cache miss rate": 0.17242613403806822, "LL cache miss rate": 0.9389869539781994 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell22", "maxwell size": 22, "matrix columns": 34914, "task clock (msec)": 35.66, "page faults": 2783, "cycles": 28797561, "instructions": 72611886, "branch mispredictions": 314831, "branches": 16822795, "ITLB accesses": 22365064, "ITLB misses": 5315, "DTLB misses": 12146, "DTLB accesses": 29931897, "L1I cache accesses": 26478185, "L1I cache misses": 232023, "L1D cache misses": 378229, "L1D cache accesses": 27831494, "LL cache misses": 448786, "LL cache accesses": 468750, "L2D TLB accesses": 130012, "L2D TLB misses": 16264, "L2D cache misses": 238552, "L2D cache accesses": 1420866, "\u0394 watt": 13.818666666666665, "branch miss rate": 0.018714547731218268, "ITLB miss rate": 0.00023764743083230168, "DTLB miss rate": 0.0004057878456550883, "L1I cache miss rate": 0.008762798507526101, "L1D cache miss rate": 0.013589963945162268, "L2D cache miss rate": 0.16789197573873962, "LL cache miss rate": 0.9574101333333334 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 38.24, "page faults": 2791, "cycles": 38107904, "instructions": 76348269, "branch mispredictions": 316120, "branches": 17064379, "ITLB accesses": 22594643, "ITLB misses": 5428, "DTLB misses": 12324, "DTLB accesses": 30768538, "L1I cache accesses": 26740932, "L1I cache misses": 233141, "L1D cache misses": 388857, "L1D cache accesses": 28098450, "LL cache misses": 466769, "LL cache accesses": 489164, "L2D TLB accesses": 133866, "L2D TLB misses": 16446, "L2D cache misses": 250317, "L2D cache accesses": 1469531, "\u0394 watt": 1.4426666666666712, "branch miss rate": 0.01852513941468365, "ITLB miss rate": 0.00024023393509691655, "DTLB miss rate": 0.00040053901813599335, "L1I cache miss rate": 0.008718506894224928, "L1D cache miss rate": 0.013839090768351991, "L2D cache miss rate": 0.17033801940891347, "LL cache miss rate": 0.9542178083423964 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell24", "maxwell size": 24, "matrix columns": 45000, "task clock (msec)": 31.53, "page faults": 2757, "cycles": 38154360, "instructions": 76003480, "branch mispredictions": 314535, "branches": 16819491, "ITLB accesses": 22654359, "ITLB misses": 5040, "DTLB misses": 11917, "DTLB accesses": 30403638, "L1I cache accesses": 26635517, "L1I cache misses": 238993, "L1D cache misses": 384206, "L1D cache accesses": 27836639, "LL cache misses": 475418, "LL cache accesses": 501247, "L2D TLB accesses": 133593, "L2D TLB misses": 17654, "L2D cache misses": 262844, "L2D cache accesses": 1466034, "\u0394 watt": 6.961333333333332, "branch miss rate": 0.01870062536375209, "ITLB miss rate": 0.00022247374114624032, "DTLB miss rate": 0.0003919596727207448, "L1I cache miss rate": 0.008972718644807984, "L1D cache miss rate": 0.013802169148365935, "L2D cache miss rate": 0.17928915700454423, "LL cache miss rate": 0.9484705145367454 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 28.84, "page faults": 3238, "cycles": 46524233, "instructions": 78604006, "branches": 17054156, "branch mispredictions": 298876, "ITLB accesses": 6035, "ITLB misses": 13621, "DTLB accesses": 17783780, "DTLB misses": 12598, "L1D cache accesses": 17494763, "L1D cache misses": 576538, "LL cache accesses": 67358, "LL cache misses": 11047, "branch miss rate": 0.01752511235384501, "ITLB miss rate": 2.257000828500414, "DTLB miss rate": 0.0007083983270148416, "L1I cache miss rate": null, "L1D cache miss rate": 0.032954890557820075, "L2D cache miss rate": null, "LL cache miss rate": 0.16400427566139136 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 27.25, "page faults": 2736, "cycles": 45435644, "instructions": 78271647, "branches": 16994482, "branch mispredictions": 291926, "ITLB accesses": 7616, "ITLB misses": 14515, "DTLB accesses": 17745451, "DTLB misses": 14184, "L1D cache accesses": 17720302, "L1D cache misses": 572377, "LL cache accesses": 63704, "LL cache misses": 11538, "branch miss rate": 0.017177693324221355, "ITLB miss rate": 1.9058560924369747, "DTLB miss rate": 0.0007993034383854205, "L1I cache miss rate": null, "L1D cache miss rate": 0.03230063460543731, "L2D cache miss rate": null, "LL cache miss rate": 0.1811189250282557 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell28", "maxwell size": 28, "matrix columns": 70644, "task clock (msec)": 37.43, "page faults": 2760, "cycles": 38247751, "instructions": 74492341, "branch mispredictions": 315870, "branches": 16808953, "ITLB accesses": 22562493, "ITLB misses": 4714, "DTLB misses": 12202, "DTLB accesses": 30307579, "L1I cache accesses": 26528925, "L1I cache misses": 229763, "L1D cache misses": 371071, "L1D cache accesses": 27793339, "LL cache misses": 473991, "LL cache accesses": 495456, "L2D TLB accesses": 134781, "L2D TLB misses": 17650, "L2D cache misses": 257771, "L2D cache accesses": 1472049, "\u0394 watt": 18.604000000000006, "branch miss rate": 0.018791771266181777, "ITLB miss rate": 0.00020893081274307764, "DTLB miss rate": 0.0004026055660862915, "L1I cache miss rate": 0.008660848488960635, "L1D cache miss rate": 0.01335107667344323, "L2D cache miss rate": 0.1751103393976695, "LL cache miss rate": 0.9566762739779112 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 35.44, "page faults": 2764, "cycles": 36127271, "instructions": 76768925, "branch mispredictions": 316239, "branches": 16877036, "ITLB accesses": 22436874, "ITLB misses": 5008, "DTLB misses": 11966, "DTLB accesses": 30170027, "L1I cache accesses": 26578511, "L1I cache misses": 230855, "L1D cache misses": 365266, "L1D cache accesses": 27855340, "LL cache misses": 459831, "LL cache accesses": 478879, "L2D TLB accesses": 134853, "L2D TLB misses": 17671, "L2D cache misses": 246499, "L2D cache accesses": 1431433, "\u0394 watt": 2.924000000000003, "branch miss rate": 0.01873782813522469, "ITLB miss rate": 0.0002232039989171397, "DTLB miss rate": 0.00039661880315851225, "L1I cache miss rate": 0.008685776264893093, "L1D cache miss rate": 0.013112961464480419, "L2D cache miss rate": 0.1722043574515887, "LL cache miss rate": 0.9602237726022649 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 34.7, "page faults": 2768, "cycles": 26451940, "instructions": 72629827, "branch mispredictions": 318871, "branches": 16901235, "ITLB accesses": 22500323, "ITLB misses": 5270, "DTLB misses": 12429, "DTLB accesses": 30168626, "L1I cache accesses": 26444828, "L1I cache misses": 226916, "L1D cache misses": 373966, "L1D cache accesses": 27747568, "LL cache misses": 463884, "LL cache accesses": 483483, "L2D TLB accesses": 134714, "L2D TLB misses": 17910, "L2D cache misses": 244944, "L2D cache accesses": 1458075, "\u0394 watt": 5.628, "branch miss rate": 0.018866727786460574, "ITLB miss rate": 0.00023421885988036706, "DTLB miss rate": 0.00041198429123023367, "L1I cache miss rate": 0.008580732686179695, "L1D cache miss rate": 0.013477433409659543, "L2D cache miss rate": 0.16799135846921454, "LL cache miss rate": 0.9594628973510961 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell48", "maxwell size": 48, "matrix columns": 345744, "task clock (msec)": 35.09, "page faults": 2777, "cycles": 35498307, "instructions": 74874275, "branch mispredictions": 309679, "branches": 16861431, "ITLB accesses": 22803677, "ITLB misses": 5037, "DTLB misses": 12129, "DTLB accesses": 30733658, "L1I cache accesses": 26477891, "L1I cache misses": 229830, "L1D cache misses": 377265, "L1D cache accesses": 27773004, "LL cache misses": 470738, "LL cache accesses": 496153, "L2D TLB accesses": 133031, "L2D TLB misses": 17983, "L2D cache misses": 258141, "L2D cache accesses": 1471401, "\u0394 watt": 14.819999999999997, "branch miss rate": 0.01836611613806681, "ITLB miss rate": 0.0002208854300120108, "DTLB miss rate": 0.0003946487593504164, "L1I cache miss rate": 0.00868007198911726, "L1D cache miss rate": 0.013583874470330973, "L2D cache miss rate": 0.17543891841856843, "LL cache miss rate": 0.9487758816332865 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 29.36, "page faults": 3257, "cycles": 47397126, "instructions": 79359110, "branches": 17182349, "branch mispredictions": 299371, "ITLB accesses": 7154, "ITLB misses": 14997, "DTLB accesses": 17594878, "DTLB misses": 14791, "L1D cache accesses": 17816160, "L1D cache misses": 574506, "LL cache accesses": 67016, "LL cache misses": 11106, "branch miss rate": 0.01742317072013844, "ITLB miss rate": 2.096309756779424, "DTLB miss rate": 0.0008406423733088687, "L1I cache miss rate": null, "L1D cache miss rate": 0.0322463426462268, "L2D cache miss rate": null, "LL cache miss rate": 0.1657216187179181 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 27.95, "page faults": 2757, "cycles": 46254053, "instructions": 78828949, "branches": 17081818, "branch mispredictions": 295191, "ITLB accesses": 7066, "ITLB misses": 14373, "DTLB accesses": 17813443, "DTLB misses": 14801, "L1D cache accesses": 17558896, "L1D cache misses": 577762, "LL cache accesses": 58576, "LL cache misses": 11107, "branch miss rate": 0.017281006038116085, "ITLB miss rate": 2.0341069912255874, "DTLB miss rate": 0.0008308893457598287, "L1I cache miss rate": null, "L1D cache miss rate": 0.03290423270346837, "L2D cache miss rate": null, "LL cache miss rate": 0.1896169079486479 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell12", "maxwell size": 12, "matrix columns": 6084, "task clock (msec)": 33.23, "page faults": 2759, "cycles": 30945071, "instructions": 69398421, "branch mispredictions": 314531, "branches": 16779111, "ITLB accesses": 22691553, "ITLB misses": 4951, "DTLB misses": 12203, "DTLB accesses": 30498706, "L1I cache accesses": 26484775, "L1I cache misses": 230256, "L1D cache misses": 382347, "L1D cache accesses": 27731498, "LL cache misses": 459487, "LL cache accesses": 479612, "L2D TLB accesses": 136168, "L2D TLB misses": 16861, "L2D cache misses": 247064, "L2D cache accesses": 1432491, "\u0394 watt": 11.930666666666667, "branch miss rate": 0.018745391218879238, "ITLB miss rate": 0.00021818691739609007, "DTLB miss rate": 0.0004001153360408143, "L1I cache miss rate": 0.008693900552298444, "L1D cache miss rate": 0.013787462905898556, "L2D cache miss rate": 0.17247158969934193, "LL cache miss rate": 0.9580389981902038 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 34.05, "page faults": 2772, "cycles": 35361566, "instructions": 75377352, "branch mispredictions": 313864, "branches": 16971197, "ITLB accesses": 22441338, "ITLB misses": 5089, "DTLB misses": 12043, "DTLB accesses": 30113443, "L1I cache accesses": 26484166, "L1I cache misses": 234493, "L1D cache misses": 375748, "L1D cache accesses": 27804002, "LL cache misses": 474052, "LL cache accesses": 502246, "L2D TLB accesses": 140197, "L2D TLB misses": 18415, "L2D cache misses": 265062, "L2D cache accesses": 1466151, "\u0394 watt": 4.187999999999999, "branch miss rate": 0.018493922379193405, "ITLB miss rate": 0.00022676900994049465, "DTLB miss rate": 0.0003999210585119742, "L1I cache miss rate": 0.008854082850862663, "L1D cache miss rate": 0.013514169650829402, "L2D cache miss rate": 0.18078765420478518, "LL cache miss rate": 0.9438641621834718 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell36", "maxwell size": 36, "matrix columns": 147852, "task clock (msec)": 33.29, "page faults": 2784, "cycles": 27771327, "instructions": 74669795, "branch mispredictions": 317060, "branches": 16860901, "ITLB accesses": 22406422, "ITLB misses": 5222, "DTLB misses": 12241, "DTLB accesses": 30325313, "L1I cache accesses": 26887951, "L1I cache misses": 242387, "L1D cache misses": 392627, "L1D cache accesses": 28111869, "LL cache misses": 471324, "LL cache accesses": 510684, "L2D TLB accesses": 136615, "L2D TLB misses": 18298, "L2D cache misses": 272960, "L2D cache accesses": 1501134, "\u0394 watt": 11.283999999999995, "branch miss rate": 0.01880445179056564, "ITLB miss rate": 0.00023305818305126985, "DTLB miss rate": 0.00040365617990488674, "L1I cache miss rate": 0.009014706996453542, "L1D cache miss rate": 0.013966591833506339, "L2D cache miss rate": 0.1818358654190765, "LL cache miss rate": 0.9229268980426252 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell46", "maxwell size": 46, "matrix columns": 304842, "task clock (msec)": 31.96, "page faults": 2806, "cycles": 27840159, "instructions": 74835856, "branch mispredictions": 312737, "branches": 16758090, "ITLB accesses": 22859003, "ITLB misses": 5584, "DTLB misses": 13002, "DTLB accesses": 30585286, "L1I cache accesses": 26237522, "L1I cache misses": 226286, "L1D cache misses": 373324, "L1D cache accesses": 27436569, "LL cache misses": 465023, "LL cache accesses": 492346, "L2D TLB accesses": 135926, "L2D TLB misses": 17901, "L2D cache misses": 256396, "L2D cache accesses": 1470740, "\u0394 watt": 14.650666666666666, "branch miss rate": 0.01866185227552782, "ITLB miss rate": 0.0002442801201784697, "DTLB miss rate": 0.0004251063730448687, "L1I cache miss rate": 0.008624518733133411, "L1D cache miss rate": 0.013606803387114475, "L2D cache miss rate": 0.17433128901097406, "LL cache miss rate": 0.9445044744955783 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 31.55, "page faults": 2771, "cycles": 28283186, "instructions": 74469098, "branch mispredictions": 311442, "branches": 16765071, "ITLB accesses": 22534328, "ITLB misses": 5621, "DTLB misses": 12662, "DTLB accesses": 30175541, "L1I cache accesses": 26702763, "L1I cache misses": 246882, "L1D cache misses": 387738, "L1D cache accesses": 27767626, "LL cache misses": 459949, "LL cache accesses": 482967, "L2D TLB accesses": 131653, "L2D TLB misses": 17297, "L2D cache misses": 245227, "L2D cache accesses": 1451665, "\u0394 watt": 3.324000000000005, "branch miss rate": 0.018576837521296508, "ITLB miss rate": 0.00024944165186554487, "DTLB miss rate": 0.0004196113667025887, "L1I cache miss rate": 0.009245560094286872, "L1D cache miss rate": 0.013963671219138432, "L2D cache miss rate": 0.16892809291399874, "LL cache miss rate": 0.9523404290562295 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 33.37, "page faults": 2779, "cycles": 36802889, "instructions": 75056728, "branch mispredictions": 313750, "branches": 16722652, "ITLB accesses": 22567618, "ITLB misses": 5618, "DTLB misses": 12389, "DTLB accesses": 30324090, "L1I cache accesses": 26480842, "L1I cache misses": 225755, "L1D cache misses": 369823, "L1D cache accesses": 27799943, "LL cache misses": 457189, "LL cache accesses": 485992, "L2D TLB accesses": 131135, "L2D TLB misses": 17503, "L2D cache misses": 250990, "L2D cache accesses": 1464593, "\u0394 watt": 6.472000000000001, "branch miss rate": 0.018761976270271007, "ITLB miss rate": 0.00024894076104974835, "DTLB miss rate": 0.00040855306787441933, "L1I cache miss rate": 0.008525219855169257, "L1D cache miss rate": 0.013303012887472467, "L2D cache miss rate": 0.17137184187006219, "LL cache miss rate": 0.9407335923225074 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell30", "maxwell size": 30, "matrix columns": 86490, "task clock (msec)": 34.81, "page faults": 2765, "cycles": 36773990, "instructions": 74420116, "branch mispredictions": 314951, "branches": 17042284, "ITLB accesses": 22487197, "ITLB misses": 5607, "DTLB misses": 12638, "DTLB accesses": 30192260, "L1I cache accesses": 27043845, "L1I cache misses": 236758, "L1D cache misses": 383812, "L1D cache accesses": 28459501, "LL cache misses": 457211, "LL cache accesses": 476767, "L2D TLB accesses": 134166, "L2D TLB misses": 16622, "L2D cache misses": 241461, "L2D cache accesses": 1434082, "\u0394 watt": 8.020000000000003, "branch miss rate": 0.01848056281658022, "ITLB miss rate": 0.00024934188107126026, "DTLB miss rate": 0.0004185841006933565, "L1I cache miss rate": 0.008754598319876482, "L1D cache miss rate": 0.013486251919877302, "L2D cache miss rate": 0.16837321715215728, "LL cache miss rate": 0.9589820604194502 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell32", "maxwell size": 32, "matrix columns": 104544, "task clock (msec)": 37.31, "page faults": 2777, "cycles": 34048763, "instructions": 74343582, "branch mispredictions": 317436, "branches": 16874761, "ITLB accesses": 22591179, "ITLB misses": 4795, "DTLB misses": 11739, "DTLB accesses": 30359421, "L1I cache accesses": 26705866, "L1I cache misses": 229557, "L1D cache misses": 377734, "L1D cache accesses": 28114986, "LL cache misses": 463225, "LL cache accesses": 483313, "L2D TLB accesses": 134440, "L2D TLB misses": 17618, "L2D cache misses": 247222, "L2D cache accesses": 1452336, "\u0394 watt": 17.98933333333333, "branch miss rate": 0.018811288645806598, "ITLB miss rate": 0.0002122509852186112, "DTLB miss rate": 0.0003866674532429324, "L1I cache miss rate": 0.008595751959513315, "L1D cache miss rate": 0.013435325914798606, "L2D cache miss rate": 0.17022369479238963, "LL cache miss rate": 0.9584368721718638 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell48", "maxwell size": 48, "matrix columns": 345744, "task clock (msec)": 34.94, "page faults": 2771, "cycles": 38735018, "instructions": 75159781, "branch mispredictions": 315149, "branches": 16816929, "ITLB accesses": 22633453, "ITLB misses": 5768, "DTLB misses": 12591, "DTLB accesses": 30399400, "L1I cache accesses": 26918987, "L1I cache misses": 244722, "L1D cache misses": 389557, "L1D cache accesses": 28286479, "LL cache misses": 462508, "LL cache accesses": 481919, "L2D TLB accesses": 136590, "L2D TLB misses": 17961, "L2D cache misses": 246707, "L2D cache accesses": 1437179, "\u0394 watt": 12.584000000000003, "branch miss rate": 0.01873998516613824, "ITLB miss rate": 0.00025484401341677735, "DTLB miss rate": 0.00041418580629880856, "L1I cache miss rate": 0.009091055320915307, "L1D cache miss rate": 0.013771844845022953, "L2D cache miss rate": 0.17166059342642775, "LL cache miss rate": 0.9597214469651539 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell34", "maxwell size": 34, "matrix columns": 124950, "task clock (msec)": 31.77, "page faults": 2772, "cycles": 21933963, "instructions": 71670947, "branch mispredictions": 313067, "branches": 16949851, "ITLB accesses": 22410986, "ITLB misses": 5228, "DTLB misses": 12020, "DTLB accesses": 30113343, "L1I cache accesses": 26523000, "L1I cache misses": 232921, "L1D cache misses": 380346, "L1D cache accesses": 27768454, "LL cache misses": 470177, "LL cache accesses": 493751, "L2D TLB accesses": 134281, "L2D TLB misses": 16783, "L2D cache misses": 257166, "L2D cache accesses": 1461513, "\u0394 watt": 17.726666666666663, "branch miss rate": 0.018470191861863564, "ITLB miss rate": 0.00023327844656187817, "DTLB miss rate": 0.0003991586055390795, "L1I cache miss rate": 0.008781849715341402, "L1D cache miss rate": 0.013697053498188987, "L2D cache miss rate": 0.17595874959716404, "LL cache miss rate": 0.9522552865715715 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell44", "maxwell size": 44, "matrix columns": 267300, "task clock (msec)": 33.08, "page faults": 2779, "cycles": 25039508, "instructions": 73874444, "branch mispredictions": 314391, "branches": 16756549, "ITLB accesses": 22832236, "ITLB misses": 5366, "DTLB misses": 12776, "DTLB accesses": 30548671, "L1I cache accesses": 26617695, "L1I cache misses": 251490, "L1D cache misses": 393877, "L1D cache accesses": 27768409, "LL cache misses": 473559, "LL cache accesses": 506336, "L2D TLB accesses": 138392, "L2D TLB misses": 18953, "L2D cache misses": 267893, "L2D cache accesses": 1496868, "\u0394 watt": 13.570666666666668, "branch miss rate": 0.018762276170349874, "ITLB miss rate": 0.00023501859388629304, "DTLB miss rate": 0.0004182178661716577, "L1I cache miss rate": 0.009448226076675685, "L1D cache miss rate": 0.014184356042868714, "L2D cache miss rate": 0.1789690206484473, "LL cache miss rate": 0.9352663053782468 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell30", "maxwell size": 30, "matrix columns": 86490, "task clock (msec)": 30.87, "page faults": 2759, "cycles": 37012840, "instructions": 73960783, "branch mispredictions": 315756, "branches": 16812678, "ITLB accesses": 22882240, "ITLB misses": 5700, "DTLB misses": 12892, "DTLB accesses": 30639838, "L1I cache accesses": 26461356, "L1I cache misses": 231196, "L1D cache misses": 378676, "L1D cache accesses": 27671660, "LL cache misses": 470732, "LL cache accesses": 496250, "L2D TLB accesses": 135873, "L2D TLB misses": 19574, "L2D cache misses": 261795, "L2D cache accesses": 1476352, "\u0394 watt": 9.581333333333337, "branch miss rate": 0.01878082718291518, "ITLB miss rate": 0.0002491014865677486, "DTLB miss rate": 0.00042075940479841965, "L1I cache miss rate": 0.008737118385013981, "L1D cache miss rate": 0.013684614511742339, "L2D cache miss rate": 0.1773255971475637, "LL cache miss rate": 0.9485783375314861 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell30", "maxwell size": 30, "matrix columns": 86490, "task clock (msec)": 38.13, "page faults": 2794, "cycles": 32415571, "instructions": 75634143, "branch mispredictions": 312624, "branches": 16735629, "ITLB accesses": 22746815, "ITLB misses": 5116, "DTLB misses": 12449, "DTLB accesses": 30413011, "L1I cache accesses": 26672713, "L1I cache misses": 231027, "L1D cache misses": 377361, "L1D cache accesses": 27757160, "LL cache misses": 469460, "LL cache accesses": 493233, "L2D TLB accesses": 136380, "L2D TLB misses": 18404, "L2D cache misses": 255871, "L2D cache accesses": 1460513, "\u0394 watt": 17.996, "branch miss rate": 0.018680146410989393, "ITLB miss rate": 0.00022491060836429187, "DTLB miss rate": 0.00040933138780635693, "L1I cache miss rate": 0.008661548602123826, "L1D cache miss rate": 0.013595086817239227, "L2D cache miss rate": 0.17519255220597146, "LL cache miss rate": 0.9518016839911361 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 31.1, "page faults": 3260, "cycles": 49512609, "instructions": 79157466, "branches": 17163022, "branch mispredictions": 296724, "ITLB accesses": 7966, "ITLB misses": 13125, "DTLB accesses": 17723474, "DTLB misses": 13123, "L1D cache accesses": 17642308, "L1D cache misses": 578691, "LL cache accesses": 70574, "LL cache misses": 30238, "branch miss rate": 0.017288563750602896, "ITLB miss rate": 1.647627416520211, "DTLB miss rate": 0.0007404304596265946, "L1I cache miss rate": null, "L1D cache miss rate": 0.032801320552843766, "L2D cache miss rate": null, "LL cache miss rate": 0.42845807237792954 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 37.94, "page faults": 2766, "cycles": 38331378, "instructions": 70059972, "branch mispredictions": 313098, "branches": 16918712, "ITLB accesses": 22604179, "ITLB misses": 5034, "DTLB misses": 12111, "DTLB accesses": 30294479, "L1I cache accesses": 26278079, "L1I cache misses": 221462, "L1D cache misses": 380684, "L1D cache accesses": 27551821, "LL cache misses": 466481, "LL cache accesses": 490057, "L2D TLB accesses": 134286, "L2D TLB misses": 18651, "L2D cache misses": 255806, "L2D cache accesses": 1444473, "\u0394 watt": 9.651999999999994, "branch miss rate": 0.01850601866146785, "ITLB miss rate": 0.00022270218263622846, "DTLB miss rate": 0.00039977581393626214, "L1I cache miss rate": 0.008427632780919793, "L1D cache miss rate": 0.01381701775719289, "L2D cache miss rate": 0.1770929605468569, "LL cache miss rate": 0.9518913106026442 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 34.09, "page faults": 2782, "cycles": 37064169, "instructions": 74037049, "branch mispredictions": 313553, "branches": 16971332, "ITLB accesses": 22830212, "ITLB misses": 5471, "DTLB misses": 12426, "DTLB accesses": 30661633, "L1I cache accesses": 26615111, "L1I cache misses": 230524, "L1D cache misses": 376346, "L1D cache accesses": 27931850, "LL cache misses": 461499, "LL cache accesses": 488022, "L2D TLB accesses": 135124, "L2D TLB misses": 18143, "L2D cache misses": 253051, "L2D cache accesses": 1454207, "\u0394 watt": 2.6693333333333378, "branch miss rate": 0.01847545024751151, "ITLB miss rate": 0.0002396385981873493, "DTLB miss rate": 0.00040526217243549946, "L1I cache miss rate": 0.008661395400530172, "L1D cache miss rate": 0.013473722649949789, "L2D cache miss rate": 0.1740130531623077, "LL cache miss rate": 0.9456520402768728 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell26", "maxwell size": 26, "matrix columns": 56862, "task clock (msec)": 35.49, "page faults": 2781, "cycles": 35904207, "instructions": 74255441, "branch mispredictions": 315604, "branches": 16831247, "ITLB accesses": 23016221, "ITLB misses": 5250, "DTLB misses": 12426, "DTLB accesses": 30958111, "L1I cache accesses": 26467387, "L1I cache misses": 233063, "L1D cache misses": 384211, "L1D cache accesses": 27694892, "LL cache misses": 464776, "LL cache accesses": 484199, "L2D TLB accesses": 134303, "L2D TLB misses": 18242, "L2D cache misses": 249032, "L2D cache accesses": 1443567, "\u0394 watt": 9.132000000000001, "branch miss rate": 0.018751076494807544, "ITLB miss rate": 0.00022809999956117905, "DTLB miss rate": 0.00040138107909749404, "L1I cache miss rate": 0.008805667140469892, "L1D cache miss rate": 0.013872991452719873, "L2D cache miss rate": 0.17251156337045664, "LL cache miss rate": 0.9598863277288884 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell44", "maxwell size": 44, "matrix columns": 267300, "task clock (msec)": 30.91, "page faults": 2746, "cycles": 33264810, "instructions": 69273601, "branch mispredictions": 315526, "branches": 16760967, "ITLB accesses": 22949528, "ITLB misses": 5982, "DTLB misses": 13101, "DTLB accesses": 30809060, "L1I cache accesses": 26535815, "L1I cache misses": 240994, "L1D cache misses": 384916, "L1D cache accesses": 27816607, "LL cache misses": 460494, "LL cache accesses": 481127, "L2D TLB accesses": 132497, "L2D TLB misses": 18586, "L2D cache misses": 246736, "L2D cache accesses": 1446914, "\u0394 watt": 18.18533333333333, "branch miss rate": 0.01882504750471736, "ITLB miss rate": 0.0002606589556003069, "DTLB miss rate": 0.00042523205836205325, "L1I cache miss rate": 0.009081839016438727, "L1D cache miss rate": 0.013837633036983986, "L2D cache miss rate": 0.1705256843184875, "LL cache miss rate": 0.9571152730983711 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell42", "maxwell size": 42, "matrix columns": 232974, "task clock (msec)": 34.51, "page faults": 2760, "cycles": 35380085, "instructions": 74882678, "branch mispredictions": 314478, "branches": 16924367, "ITLB accesses": 22759319, "ITLB misses": 5648, "DTLB misses": 12671, "DTLB accesses": 30491137, "L1I cache accesses": 26636435, "L1I cache misses": 235128, "L1D cache misses": 384387, "L1D cache accesses": 27971398, "LL cache misses": 465165, "LL cache accesses": 484747, "L2D TLB accesses": 132302, "L2D TLB misses": 17635, "L2D cache misses": 248647, "L2D cache accesses": 1440208, "\u0394 watt": 18.493333333333336, "branch miss rate": 0.018581374417134772, "ITLB miss rate": 0.000248162082529798, "DTLB miss rate": 0.0004155633815819987, "L1I cache miss rate": 0.008827307408067184, "L1D cache miss rate": 0.013742144743712846, "L2D cache miss rate": 0.1726465899370091, "LL cache miss rate": 0.9596036695430812 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 35.58, "page faults": 2792, "cycles": 28042392, "instructions": 75410629, "branch mispredictions": 313846, "branches": 16941333, "ITLB accesses": 22593698, "ITLB misses": 5385, "DTLB misses": 12202, "DTLB accesses": 30439426, "L1I cache accesses": 26430404, "L1I cache misses": 229508, "L1D cache misses": 380816, "L1D cache accesses": 27753131, "LL cache misses": 457586, "LL cache accesses": 478259, "L2D TLB accesses": 132482, "L2D TLB misses": 17723, "L2D cache misses": 242435, "L2D cache accesses": 1426434, "\u0394 watt": 4.026666666666667, "branch miss rate": 0.018525460776905808, "ITLB miss rate": 0.00023834079750911072, "DTLB miss rate": 0.00040086169824621526, "L1I cache miss rate": 0.008683484368986565, "L1D cache miss rate": 0.013721550912579917, "L2D cache miss rate": 0.16995879234510675, "LL cache miss rate": 0.9567744673910998 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell40", "maxwell size": 40, "matrix columns": 201720, "task clock (msec)": 31.72, "page faults": 2785, "cycles": 30090507, "instructions": 74992863, "branch mispredictions": 317814, "branches": 16791616, "ITLB accesses": 22677480, "ITLB misses": 5557, "DTLB misses": 12446, "DTLB accesses": 30413594, "L1I cache accesses": 26843425, "L1I cache misses": 239555, "L1D cache misses": 385295, "L1D cache accesses": 27801251, "LL cache misses": 476478, "LL cache accesses": 505239, "L2D TLB accesses": 136570, "L2D TLB misses": 19385, "L2D cache misses": 267638, "L2D cache accesses": 1488002, "\u0394 watt": 12.689333333333337, "branch miss rate": 0.0189269454470612, "ITLB miss rate": 0.0002450448638914024, "DTLB miss rate": 0.0004092249012070063, "L1I cache miss rate": 0.008924159268051674, "L1D cache miss rate": 0.013858908723208175, "L2D cache miss rate": 0.17986400555913232, "LL cache miss rate": 0.9430744657478936 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 34.04, "page faults": 3255, "cycles": 54898600, "instructions": 81271980, "branches": 17559162, "branch mispredictions": 300852, "ITLB accesses": 7217, "ITLB misses": 13929, "DTLB accesses": 17787712, "DTLB misses": 12504, "L1D cache accesses": 17720101, "L1D cache misses": 590640, "LL cache accesses": 79901, "LL cache misses": 28153, "branch miss rate": 0.017133619474551234, "ITLB miss rate": 1.9300263267285576, "DTLB miss rate": 0.0007029571875236118, "L1I cache miss rate": null, "L1D cache miss rate": 0.033331638459622774, "L2D cache miss rate": null, "LL cache miss rate": 0.352348531307493 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell14", "maxwell size": 14, "matrix columns": 9450, "task clock (msec)": 32.29, "page faults": 2770, "cycles": 24172523, "instructions": 55925355, "branch mispredictions": 316558, "branches": 16867022, "ITLB accesses": 22725421, "ITLB misses": 5397, "DTLB misses": 12729, "DTLB accesses": 30412650, "L1I cache accesses": 26252660, "L1I cache misses": 230453, "L1D cache misses": 372224, "L1D cache accesses": 27429044, "LL cache misses": 468447, "LL cache accesses": 497410, "L2D TLB accesses": 134272, "L2D TLB misses": 17416, "L2D cache misses": 260097, "L2D cache accesses": 1447346, "\u0394 watt": 2.3826666666666654, "branch miss rate": 0.018767865483308197, "ITLB miss rate": 0.00023748734951928944, "DTLB miss rate": 0.0004185429418350588, "L1I cache miss rate": 0.008778272373161424, "L1D cache miss rate": 0.013570432859417192, "L2D cache miss rate": 0.17970616563005667, "LL cache miss rate": 0.9417723809332341 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell6", "maxwell size": 6, "matrix columns": 882, "task clock (msec)": 40.34, "page faults": 2792, "cycles": 40725361, "instructions": 68488967, "branch mispredictions": 313193, "branches": 17140574, "ITLB accesses": 22851908, "ITLB misses": 5193, "DTLB misses": 12545, "DTLB accesses": 30844809, "L1I cache accesses": 26633420, "L1I cache misses": 229672, "L1D cache misses": 383161, "L1D cache accesses": 27956131, "LL cache misses": 463797, "LL cache accesses": 489201, "L2D TLB accesses": 135365, "L2D TLB misses": 18059, "L2D cache misses": 259969, "L2D cache accesses": 1489942, "\u0394 watt": 5.204000000000001, "branch miss rate": 0.018272025195889007, "ITLB miss rate": 0.0002272457949681926, "DTLB miss rate": 0.0004067134926982365, "L1I cache miss rate": 0.00862345128789318, "L1D cache miss rate": 0.013705794982860826, "L2D cache miss rate": 0.17448263086751029, "LL cache miss rate": 0.9480704250400143 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 27.37, "page faults": 2743, "cycles": 45221267, "instructions": 77850447, "branches": 16924518, "branch mispredictions": 289895, "ITLB accesses": 7777, "ITLB misses": 13661, "DTLB accesses": 17612621, "DTLB misses": 13387, "L1D cache accesses": 17644914, "L1D cache misses": 585931, "LL cache accesses": 63994, "LL cache misses": 11514, "branch miss rate": 0.01712870050420343, "ITLB miss rate": 1.7565899447087565, "DTLB miss rate": 0.0007600799449440262, "L1I cache miss rate": null, "L1D cache miss rate": 0.03320679262024173, "L2D cache miss rate": null, "LL cache miss rate": 0.17992311779229303 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell42", "maxwell size": 42, "matrix columns": 232974, "task clock (msec)": 36.28, "page faults": 2767, "cycles": 36494687, "instructions": 75735617, "branch mispredictions": 318923, "branches": 16870425, "ITLB accesses": 22620706, "ITLB misses": 5106, "DTLB misses": 12161, "DTLB accesses": 30340073, "L1I cache accesses": 26386929, "L1I cache misses": 231708, "L1D cache misses": 380332, "L1D cache accesses": 27654763, "LL cache misses": 463631, "LL cache accesses": 486406, "L2D TLB accesses": 135704, "L2D TLB misses": 17865, "L2D cache misses": 252089, "L2D cache accesses": 1453983, "\u0394 watt": 10.441333333333336, "branch miss rate": 0.01890426589727289, "ITLB miss rate": 0.00022572239787741372, "DTLB miss rate": 0.00040082303032032917, "L1I cache miss rate": 0.008781165856777042, "L1D cache miss rate": 0.013752856967170537, "L2D cache miss rate": 0.17337823069458172, "LL cache miss rate": 0.9531769756129653 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 31.43, "page faults": 2786, "cycles": 32825625, "instructions": 75014125, "branch mispredictions": 313433, "branches": 16808190, "ITLB accesses": 22734099, "ITLB misses": 5182, "DTLB misses": 12290, "DTLB accesses": 30370350, "L1I cache accesses": 26524678, "L1I cache misses": 233449, "L1D cache misses": 385270, "L1D cache accesses": 27778791, "LL cache misses": 460456, "LL cache accesses": 481548, "L2D TLB accesses": 130326, "L2D TLB misses": 16370, "L2D cache misses": 244717, "L2D cache accesses": 1437795, "\u0394 watt": 2.287999999999993, "branch miss rate": 0.01864763546818545, "ITLB miss rate": 0.00022793953699242712, "DTLB miss rate": 0.0004046710031329899, "L1I cache miss rate": 0.008801200150290232, "L1D cache miss rate": 0.013869214106546249, "L2D cache miss rate": 0.1702029844310211, "LL cache miss rate": 0.9561995896566905 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 32.1, "page faults": 3258, "cycles": 52669502, "instructions": 78956410, "branches": 17149756, "branch mispredictions": 297161, "ITLB accesses": 8246, "ITLB misses": 13925, "DTLB accesses": 17627282, "DTLB misses": 13397, "L1D cache accesses": 17704168, "L1D cache misses": 585596, "LL cache accesses": 63570, "LL cache misses": 21995, "branch miss rate": 0.017327418535867216, "ITLB miss rate": 1.6886975503274315, "DTLB miss rate": 0.0007600150720910915, "L1I cache miss rate": null, "L1D cache miss rate": 0.0330767308579539, "L2D cache miss rate": null, "LL cache miss rate": 0.345996539248073 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell36", "maxwell size": 36, "matrix columns": 147852, "task clock (msec)": 33.27, "page faults": 2753, "cycles": 35426575, "instructions": 71870191, "branch mispredictions": 316778, "branches": 16824789, "ITLB accesses": 22734331, "ITLB misses": 5919, "DTLB misses": 13018, "DTLB accesses": 30547018, "L1I cache accesses": 26772573, "L1I cache misses": 239661, "L1D cache misses": 388417, "L1D cache accesses": 28077546, "LL cache misses": 470825, "LL cache accesses": 499788, "L2D TLB accesses": 134784, "L2D TLB misses": 17541, "L2D cache misses": 259055, "L2D cache accesses": 1481192, "\u0394 watt": 18.52133333333333, "branch miss rate": 0.018828051870368182, "ITLB miss rate": 0.00026035514306534905, "DTLB miss rate": 0.0004261627108741023, "L1I cache miss rate": 0.008951735793194027, "L1D cache miss rate": 0.013833723217833924, "L2D cache miss rate": 0.1748962997369686, "LL cache miss rate": 0.9420494289578781 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 30.27, "page faults": 2770, "cycles": 50550862, "instructions": 79719924, "branches": 17279759, "branch mispredictions": 296867, "ITLB accesses": 7116, "ITLB misses": 13736, "DTLB accesses": 17549541, "DTLB misses": 12086, "L1D cache accesses": 18242451, "L1D cache misses": 585771, "LL cache accesses": 74593, "LL cache misses": 27394, "branch miss rate": 0.017180042846662386, "ITLB miss rate": 1.9302979201798762, "DTLB miss rate": 0.0006886789802650679, "L1I cache miss rate": null, "L1D cache miss rate": 0.03211032333319684, "L2D cache miss rate": null, "LL cache miss rate": 0.3672462563511321 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 36.52, "page faults": 2774, "cycles": 27452119, "instructions": 75842779, "branch mispredictions": 310172, "branches": 16670816, "ITLB accesses": 22606324, "ITLB misses": 4704, "DTLB misses": 11949, "DTLB accesses": 30316550, "L1I cache accesses": 26555286, "L1I cache misses": 223942, "L1D cache misses": 370100, "L1D cache accesses": 27948620, "LL cache misses": 457578, "LL cache accesses": 478311, "L2D TLB accesses": 133288, "L2D TLB misses": 16236, "L2D cache misses": 243738, "L2D cache accesses": 1421114, "\u0394 watt": 3.8346666666666636, "branch miss rate": 0.018605687927933462, "ITLB miss rate": 0.00020808336640667453, "DTLB miss rate": 0.0003941411539241767, "L1I cache miss rate": 0.008433047943825572, "L1D cache miss rate": 0.013242156500034706, "L2D cache miss rate": 0.17151192655902342, "LL cache miss rate": 0.9566537252958849 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 27.88, "page faults": 2760, "cycles": 46921016, "instructions": 78144329, "branches": 16979990, "branch mispredictions": 290347, "ITLB accesses": 8645, "ITLB misses": 14952, "DTLB accesses": 18158039, "DTLB misses": 13996, "L1D cache accesses": 17789454, "L1D cache misses": 588225, "LL cache accesses": 72251, "LL cache misses": 22822, "branch miss rate": 0.017099362249329945, "ITLB miss rate": 1.7295546558704453, "DTLB miss rate": 0.0007707880790431169, "L1I cache miss rate": null, "L1D cache miss rate": 0.033065938954618845, "L2D cache miss rate": null, "LL cache miss rate": 0.31587106060815767 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell38", "maxwell size": 38, "matrix columns": 173394, "task clock (msec)": 38.61, "page faults": 2766, "cycles": 39328079, "instructions": 75494594, "branch mispredictions": 310994, "branches": 16926326, "ITLB accesses": 22675910, "ITLB misses": 5189, "DTLB misses": 12161, "DTLB accesses": 30479301, "L1I cache accesses": 26347950, "L1I cache misses": 229528, "L1D cache misses": 378890, "L1D cache accesses": 27541548, "LL cache misses": 463900, "LL cache accesses": 489009, "L2D TLB accesses": 134701, "L2D TLB misses": 18706, "L2D cache misses": 254272, "L2D cache accesses": 1461379, "\u0394 watt": 19.607999999999997, "branch miss rate": 0.0183733906578427, "ITLB miss rate": 0.00022883315377420356, "DTLB miss rate": 0.00039899208974641514, "L1I cache miss rate": 0.00871141777633554, "L1D cache miss rate": 0.013757033555267119, "L2D cache miss rate": 0.17399456266991656, "LL cache miss rate": 0.9486532967695891 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell8", "maxwell size": 8, "matrix columns": 1944, "task clock (msec)": 27.22, "page faults": 2725, "cycles": 44632551, "instructions": 77896058, "branches": 16923307, "branch mispredictions": 294777, "ITLB accesses": 7728, "ITLB misses": 15145, "DTLB accesses": 17770114, "DTLB misses": 14254, "L1D cache accesses": 17635810, "L1D cache misses": 580270, "LL cache accesses": 67584, "LL cache misses": 10728, "branch miss rate": 0.017418404097969742, "ITLB miss rate": 1.9597567287784678, "DTLB miss rate": 0.0008021332896344953, "L1I cache miss rate": null, "L1D cache miss rate": 0.03290294009744945, "L2D cache miss rate": null, "LL cache miss rate": 0.15873579545454544 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell4", "maxwell size": 4, "matrix columns": 300, "task clock (msec)": 28.86, "page faults": 3264, "cycles": 46795526, "instructions": 78858968, "branches": 17090137, "branch mispredictions": 298327, "ITLB accesses": 7578, "ITLB misses": 14795, "DTLB accesses": 17888783, "DTLB misses": 14186, "L1D cache accesses": 17505349, "L1D cache misses": 581950, "LL cache accesses": 64296, "LL cache misses": 10879, "branch miss rate": 0.017456091779720666, "ITLB miss rate": 1.9523621008181578, "DTLB miss rate": 0.000793010905213619, "L1I cache miss rate": null, "L1D cache miss rate": 0.033244124410201706, "L2D cache miss rate": null, "LL cache miss rate": 0.16920181659823316 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell46", "maxwell size": 46, "matrix columns": 304842, "task clock (msec)": 35.3, "page faults": 2767, "cycles": 22305313, "instructions": 76129183, "branch mispredictions": 314288, "branches": 16855761, "ITLB accesses": 22706804, "ITLB misses": 4706, "DTLB misses": 11592, "DTLB accesses": 30488173, "L1I cache accesses": 26439331, "L1I cache misses": 237296, "L1D cache misses": 383050, "L1D cache accesses": 27780593, "LL cache misses": 466156, "LL cache accesses": 496369, "L2D TLB accesses": 136658, "L2D TLB misses": 17239, "L2D cache misses": 257674, "L2D cache accesses": 1463558, "\u0394 watt": 18.817333333333327, "branch miss rate": 0.018645731865799473, "ITLB miss rate": 0.00020725065491383112, "DTLB miss rate": 0.00038021300915604226, "L1I cache miss rate": 0.00897511362900975, "L1D cache miss rate": 0.013788402572976035, "L2D cache miss rate": 0.1760599853234378, "LL cache miss rate": 0.9391319764127091 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell44", "maxwell size": 44, "matrix columns": 267300, "task clock (msec)": 36.17, "page faults": 2781, "cycles": 36947128, "instructions": 75251973, "branch mispredictions": 312703, "branches": 16944024, "ITLB accesses": 22792073, "ITLB misses": 4719, "DTLB misses": 12077, "DTLB accesses": 30650016, "L1I cache accesses": 26770419, "L1I cache misses": 239352, "L1D cache misses": 383301, "L1D cache accesses": 28060808, "LL cache misses": 465431, "LL cache accesses": 487524, "L2D TLB accesses": 137926, "L2D TLB misses": 19434, "L2D cache misses": 256811, "L2D cache accesses": 1462171, "\u0394 watt": 11.313333333333329, "branch miss rate": 0.01845506120624003, "ITLB miss rate": 0.0002070456689042721, "DTLB miss rate": 0.00039402915809244604, "L1I cache miss rate": 0.00894091347617682, "L1D cache miss rate": 0.013659656557288015, "L2D cache miss rate": 0.17563677572595818, "LL cache miss rate": 0.9546832566191613 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell28", "maxwell size": 28, "matrix columns": 70644, "task clock (msec)": 34.62, "page faults": 2762, "cycles": 31974608, "instructions": 73403059, "branch mispredictions": 315130, "branches": 16935603, "ITLB accesses": 22470994, "ITLB misses": 5196, "DTLB misses": 12525, "DTLB accesses": 30180086, "L1I cache accesses": 26316075, "L1I cache misses": 227022, "L1D cache misses": 373950, "L1D cache accesses": 27566086, "LL cache misses": 469059, "LL cache accesses": 494454, "L2D TLB accesses": 137297, "L2D TLB misses": 17492, "L2D cache misses": 256015, "L2D cache accesses": 1464510, "\u0394 watt": 8.707999999999995, "branch miss rate": 0.018607545299686112, "ITLB miss rate": 0.00023123142661156867, "DTLB miss rate": 0.0004150087577616578, "L1I cache miss rate": 0.008626742399844962, "L1D cache miss rate": 0.013565581998111738, "L2D cache miss rate": 0.174812736000437, "LL cache miss rate": 0.948640318411824 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 36.02, "page faults": 2754, "cycles": 28216835, "instructions": 72213172, "branch mispredictions": 310681, "branches": 16784941, "ITLB accesses": 22988923, "ITLB misses": 6290, "DTLB misses": 13349, "DTLB accesses": 30916878, "L1I cache accesses": 26592108, "L1I cache misses": 231135, "L1D cache misses": 376017, "L1D cache accesses": 27882306, "LL cache misses": 442447, "LL cache accesses": 466619, "L2D TLB accesses": 159723, "L2D TLB misses": 20452, "L2D cache misses": 246420, "L2D cache accesses": 1483875, "\u0394 watt": 4.84, "branch miss rate": 0.018509508016739527, "ITLB miss rate": 0.0002736100338410808, "DTLB miss rate": 0.0004317706335031629, "L1I cache miss rate": 0.008691864518600783, "L1D cache miss rate": 0.01348586447620222, "L2D cache miss rate": 0.16606520090978014, "LL cache miss rate": 0.9481975658942307 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell22", "maxwell size": 22, "matrix columns": 34914, "task clock (msec)": 40.05, "page faults": 2787, "cycles": 35617476, "instructions": 70762281, "branch mispredictions": 315551, "branches": 17092160, "ITLB accesses": 22270930, "ITLB misses": 5115, "DTLB misses": 12145, "DTLB accesses": 29954782, "L1I cache accesses": 26790202, "L1I cache misses": 235685, "L1D cache misses": 385839, "L1D cache accesses": 28190052, "LL cache misses": 463555, "LL cache accesses": 488806, "L2D TLB accesses": 132085, "L2D TLB misses": 17078, "L2D cache misses": 248234, "L2D cache accesses": 1456769, "\u0394 watt": 5.119999999999997, "branch miss rate": 0.01846173918334488, "ITLB miss rate": 0.0002296715943159985, "DTLB miss rate": 0.00040544444623232445, "L1I cache miss rate": 0.00879743273305666, "L1D cache miss rate": 0.01368706237221556, "L2D cache miss rate": 0.17040038605983515, "LL cache miss rate": 0.9483414688035744 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell24", "maxwell size": 24, "matrix columns": 45000, "task clock (msec)": 32.53, "page faults": 2785, "cycles": 29159609, "instructions": 70314265, "branch mispredictions": 316033, "branches": 16873830, "ITLB accesses": 23069521, "ITLB misses": 5362, "DTLB misses": 12762, "DTLB accesses": 30842612, "L1I cache accesses": 26686872, "L1I cache misses": 224715, "L1D cache misses": 377368, "L1D cache accesses": 28139495, "LL cache misses": 474128, "LL cache accesses": 497388, "L2D TLB accesses": 133601, "L2D TLB misses": 18428, "L2D cache misses": 255989, "L2D cache accesses": 1466756, "\u0394 watt": 17.632, "branch miss rate": 0.018729180037964113, "ITLB miss rate": 0.0002324278861273279, "DTLB miss rate": 0.0004137781845454594, "L1I cache miss rate": 0.008420432338417182, "L1D cache miss rate": 0.013410617354717986, "L2D cache miss rate": 0.174527324244796, "LL cache miss rate": 0.9532357033141129 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell28", "maxwell size": 28, "matrix columns": 70644, "task clock (msec)": 34.13, "page faults": 2773, "cycles": 34485952, "instructions": 69695625, "branch mispredictions": 311099, "branches": 16943287, "ITLB accesses": 22528950, "ITLB misses": 5140, "DTLB misses": 12133, "DTLB accesses": 30222074, "L1I cache accesses": 26470998, "L1I cache misses": 234215, "L1D cache misses": 384868, "L1D cache accesses": 27702279, "LL cache misses": 460126, "LL cache accesses": 479561, "L2D TLB accesses": 130255, "L2D TLB misses": 17812, "L2D cache misses": 247457, "L2D cache accesses": 1447544, "\u0394 watt": 8.194666666666663, "branch miss rate": 0.018361195203740573, "ITLB miss rate": 0.0002281508902989265, "DTLB miss rate": 0.0004014615277561692, "L1I cache miss rate": 0.008847985255410468, "L1D cache miss rate": 0.01389300858604449, "L2D cache miss rate": 0.17094955317420404, "LL cache miss rate": 0.9594733516695477 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell26", "maxwell size": 26, "matrix columns": 56862, "task clock (msec)": 35.57, "page faults": 2796, "cycles": 37717911, "instructions": 75108757, "branch mispredictions": 316034, "branches": 16843206, "ITLB accesses": 22751785, "ITLB misses": 5292, "DTLB misses": 12280, "DTLB accesses": 30599970, "L1I cache accesses": 26975818, "L1I cache misses": 232896, "L1D cache misses": 377624, "L1D cache accesses": 28434417, "LL cache misses": 466672, "LL cache accesses": 488601, "L2D TLB accesses": 133066, "L2D TLB misses": 18879, "L2D cache misses": 253862, "L2D cache accesses": 1461320, "\u0394 watt": 16.958666666666666, "branch miss rate": 0.01876329245156771, "ITLB miss rate": 0.00023259713468635538, "DTLB miss rate": 0.0004013075829812905, "L1I cache miss rate": 0.008633510205325377, "L1D cache miss rate": 0.013280525498377547, "L2D cache miss rate": 0.17372101935236636, "LL cache miss rate": 0.9551187983651281 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell38", "maxwell size": 38, "matrix columns": 173394, "task clock (msec)": 35.22, "page faults": 2756, "cycles": 31538730, "instructions": 73781559, "branch mispredictions": 312797, "branches": 16857034, "ITLB accesses": 22645562, "ITLB misses": 5056, "DTLB misses": 11917, "DTLB accesses": 30422134, "L1I cache accesses": 26428674, "L1I cache misses": 230943, "L1D cache misses": 380047, "L1D cache accesses": 27805181, "LL cache misses": 468580, "LL cache accesses": 494026, "L2D TLB accesses": 140074, "L2D TLB misses": 17751, "L2D cache misses": 258749, "L2D cache accesses": 1471487, "\u0394 watt": 14.814666666666668, "branch miss rate": 0.0185558740642037, "ITLB miss rate": 0.00022326670453133379, "DTLB miss rate": 0.00039172136971061926, "L1I cache miss rate": 0.008738349869539426, "L1D cache miss rate": 0.013668208094023917, "L2D cache miss rate": 0.17584185249343012, "LL cache miss rate": 0.9484925894588544 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 29.75, "page faults": 3246, "cycles": 47621399, "instructions": 78692838, "branches": 17085498, "branch mispredictions": 288198, "ITLB accesses": 8421, "ITLB misses": 14846, "DTLB accesses": 17760798, "DTLB misses": 14557, "L1D cache accesses": 17689718, "L1D cache misses": 591509, "LL cache accesses": 70978, "LL cache misses": 26071, "branch miss rate": 0.016867989449297877, "ITLB miss rate": 1.7629735185844913, "DTLB miss rate": 0.0008196140736469161, "L1I cache miss rate": null, "L1D cache miss rate": 0.03343801184394234, "L2D cache miss rate": null, "LL cache miss rate": 0.36731099777395815 }, { "cpu": "xeon", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 28.3, "page faults": 3228, "cycles": 46109998, "instructions": 78109004, "branches": 16948597, "branch mispredictions": 294052, "ITLB accesses": 7273, "ITLB misses": 14863, "DTLB accesses": 17646854, "DTLB misses": 14459, "L1D cache accesses": 17507990, "L1D cache misses": 578301, "LL cache accesses": 59964, "LL cache misses": 11600, "branch miss rate": 0.017349636669041102, "ITLB miss rate": 2.0435858655300425, "DTLB miss rate": 0.0008193528432886678, "L1I cache miss rate": null, "L1D cache miss rate": 0.033030690558996205, "L2D cache miss rate": null, "LL cache miss rate": 0.1934494029751184 }, { "cpu": "altra", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell40", "maxwell size": 40, "matrix columns": 201720, "task clock (msec)": 36.03, "page faults": 2758, "cycles": 24833611, "instructions": 72242583, "branch mispredictions": 316428, "branches": 17120995, "ITLB accesses": 22494089, "ITLB misses": 5243, "DTLB misses": 12074, "DTLB accesses": 30209485, "L1I cache accesses": 26372293, "L1I cache misses": 222761, "L1D cache misses": 371370, "L1D cache accesses": 27608736, "LL cache misses": 464046, "LL cache accesses": 483309, "L2D TLB accesses": 133913, "L2D TLB misses": 18047, "L2D cache misses": 246764, "L2D cache accesses": 1439307, "\u0394 watt": 9.798666666666662, "branch miss rate": 0.018481869774507848, "ITLB miss rate": 0.00023308345583588648, "DTLB miss rate": 0.00039967579718753896, "L1I cache miss rate": 0.008446781627975998, "L1D cache miss rate": 0.013451177192610339, "L2D cache miss rate": 0.1714463974676702, "LL cache miss rate": 0.960143510673296 }, { "cpu": "xeon", "solver": "MueLu", "linear algebra": "Tpetra", "input file": "maxwell20", "maxwell size": 20, "matrix columns": 26460, "task clock (msec)": 27.06, "page faults": 3249, "cycles": 45317452, "instructions": 78195120, "branches": 16987959, "branch mispredictions": 292943, "ITLB accesses": 6881, "ITLB misses": 15043, "DTLB accesses": 17690532, "DTLB misses": 12893, "L1D cache accesses": 17748819, "L1D cache misses": 581005, "LL cache accesses": 68511, "LL cache misses": 10893, "branch miss rate": 0.017244155110098865, "ITLB miss rate": 2.1861648016276702, "DTLB miss rate": 0.000728807929574984, "L1I cache miss rate": null, "L1D cache miss rate": 0.03273485407676984, "L2D cache miss rate": null, "LL cache miss rate": 0.15899636554713842 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell18", "maxwell size": 18, "matrix columns": 19494, "task clock (msec)": 35.48, "page faults": 2788, "cycles": 36826095, "instructions": 75072991, "branch mispredictions": 315151, "branches": 16739311, "ITLB accesses": 22682355, "ITLB misses": 5397, "DTLB misses": 12486, "DTLB accesses": 30580327, "L1I cache accesses": 27053327, "L1I cache misses": 231094, "L1D cache misses": 379632, "L1D cache accesses": 28510815, "LL cache misses": 466540, "LL cache accesses": 494474, "L2D TLB accesses": 134552, "L2D TLB misses": 18143, "L2D cache misses": 259011, "L2D cache accesses": 1466702, "\u0394 watt": 3.5280000000000022, "branch miss rate": 0.018826999510314375, "ITLB miss rate": 0.00023793825641120597, "DTLB miss rate": 0.00040830171632893266, "L1I cache miss rate": 0.008542165627170367, "L1D cache miss rate": 0.013315368220796214, "L2D cache miss rate": 0.17659415477718038, "LL cache miss rate": 0.9435076465092199 }, { "cpu": "altra", "solver": "GMRES", "linear algebra": "Tpetra", "input file": "maxwell48", "maxwell size": 48, "matrix columns": 345744, "task clock (msec)": 38.13, "page faults": 2785, "cycles": 36679069, "instructions": 71192944, "branch mispredictions": 317233, "branches": 16868458, "ITLB accesses": 22579878, "ITLB misses": 4892, "DTLB misses": 11824, "DTLB accesses": 30360988, "L1I cache accesses": 26394281, "L1I cache misses": 232559, "L1D cache misses": 379066, "L1D cache accesses": 27646747, "LL cache misses": 465751, "LL cache accesses": 494631, "L2D TLB accesses": 135055, "L2D TLB misses": 18439, "L2D cache misses": 258333, "L2D cache accesses": 1471965, "\u0394 watt": 19.902666666666676, "branch miss rate": 0.018806283301058106, "ITLB miss rate": 0.00021665307491918246, "DTLB miss rate": 0.00038944714183873066, "L1I cache miss rate": 0.008810961738264437, "L1D cache miss rate": 0.01371105251550933, "L2D cache miss rate": 0.1755021349013054, "LL cache miss rate": 0.9416130408324589 }, { "cpu": "altra", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell16", "maxwell size": 16, "matrix columns": 13872, "task clock (msec)": 32.59, "page faults": 2776, "cycles": 38897101, "instructions": 74428793, "branch mispredictions": 315899, "branches": 16920579, "ITLB accesses": 22862806, "ITLB misses": 5589, "DTLB misses": 12828, "DTLB accesses": 30658803, "L1I cache accesses": 26893912, "L1I cache misses": 251443, "L1D cache misses": 389567, "L1D cache accesses": 28166555, "LL cache misses": 471274, "LL cache accesses": 499214, "L2D TLB accesses": 135744, "L2D TLB misses": 17687, "L2D cache misses": 261748, "L2D cache accesses": 1495657, "\u0394 watt": 2.847999999999999, "branch miss rate": 0.018669514796154436, "ITLB miss rate": 0.0002444581824295758, "DTLB miss rate": 0.00041841163857571346, "L1I cache miss rate": 0.009349439382414875, "L1D cache miss rate": 0.013830835897396754, "L2D cache miss rate": 0.17500536553501236, "LL cache miss rate": 0.9440320183328192 }, { "cpu": "xeon", "solver": "CG", "linear algebra": "Tpetra", "input file": "maxwell10", "maxwell size": 10, "matrix columns": 3630, "task clock (msec)": 31.81, "page faults": 3265, "cycles": 50932477, "instructions": 78802385, "branches": 17089783, "branch mispredictions": 291874, "ITLB accesses": 11277, "ITLB misses": 13728, "DTLB accesses": 17681908, "DTLB misses": 12396, "L1D cache accesses": 18127571, "L1D cache misses": 590459, "LL cache accesses": 75543, "LL cache misses": 25465, "branch miss rate": 0.017078859339524674, "ITLB miss rate": 1.217345038574089, "DTLB miss rate": 0.0007010555648180049, "L1I cache miss rate": null, "L1D cache miss rate": 0.03257242793311912, "L2D cache miss rate": null, "LL cache miss rate": 0.3370927815945885 } ]