[
  {
    "power_before": [
      29.76,
      33.16
    ],
    "shape": [
      22687,
      22687
    ],
    "nnz": 54705,
    "% density": 0.00010628522108964806,
    "time_s": 0.14322686195373535,
    "power": [
      22.6,
      22.6,
      26.16,
      29.2
    ],
    "power_after": [
      34.0,
      30.16
    ],
    "task clock (msec)": 64.71,
    "page faults": 3319,
    "cycles": 57611295,
    "instructions": 83148228,
    "branch mispredictions": 318386,
    "branches": 19233431,
    "ITLB accesses": 27039805,
    "ITLB misses": 6375,
    "DTLB misses": 17290,
    "DTLB accesses": 36688544,
    "L1I cache accesses": 32508072,
    "L1I cache misses": 297568,
    "L1D cache misses": 477654,
    "L1D cache accesses": 34044579,
    "LL cache misses": 549474,
    "LL cache accesses": 561939,
    "L2D TLB accesses": 185622,
    "L2D TLB misses": 23295,
    "L2D cache misses": 305878,
    "L2D cache accesses": 1763089,
    "instructions per cycle": 1.4432626102225268,
    "branch miss rate": 0.01655378075809771,
    "ITLB miss rate": 0.00023576353453732377,
    "DTLB miss rate": 0.00047126427257511227,
    "L2D TLB miss rate": 0.12549697772893298,
    "L1I cache miss rate": 0.009153664972810446,
    "L1D cache miss rate": 0.014030251336049713,
    "L2D cache miss rate": 0.17348982382625042,
    "LL cache miss rate": 0.9778178770293573,
    "architecture": "altra"
  },
  {
    "power_before": [
      20.48,
      20.96
    ],
    "shape": [
      24115,
      24115
    ],
    "nnz": 116056,
    "% density": 0.0001995689928120616,
    "time_s": 0.3271017074584961,
    "power": [
      25.28,
      26.08,
      31.28,
      32.96
    ],
    "power_after": [
      33.4,
      30.24
    ],
    "task clock (msec)": 59.88,
    "page faults": 3313,
    "cycles": 58169777,
    "instructions": 57993431,
    "branch mispredictions": 330494,
    "branches": 20578427,
    "ITLB accesses": 27982097,
    "ITLB misses": 6614,
    "DTLB misses": 17270,
    "DTLB accesses": 37728899,
    "L1I cache accesses": 29754926,
    "L1I cache misses": 278786,
    "L1D cache misses": 454742,
    "L1D cache accesses": 31173246,
    "LL cache misses": 543243,
    "LL cache accesses": 560716,
    "L2D TLB accesses": 162281,
    "L2D TLB misses": 19847,
    "L2D cache misses": 300577,
    "L2D cache accesses": 1696278,
    "instructions per cycle": 0.9969684257170179,
    "branch miss rate": 0.016060216847478187,
    "ITLB miss rate": 0.0002363654160729984,
    "DTLB miss rate": 0.00045773930482307474,
    "L2D TLB miss rate": 0.12230020766448321,
    "L1I cache miss rate": 0.009369406598423401,
    "L1D cache miss rate": 0.014587572946365611,
    "L2D cache miss rate": 0.1771979592967662,
    "LL cache miss rate": 0.9688380570556218,
    "architecture": "altra"
  },
  {
    "power_before": [
      20.28,
      20.32
    ],
    "shape": [
      36692,
      36692
    ],
    "nnz": 367662,
    "% density": 0.0002730901120626302,
    "time_s": 1.030203104019165,
    "power": [
      32.08,
      47.84,
      55.76,
      58.08,
      58.24
    ],
    "power_after": [
      48.76,
      45.16
    ],
    "task clock (msec)": 60.43,
    "page faults": 3319,
    "cycles": 66114448,
    "instructions": 90786829,
    "branch mispredictions": 341625,
    "branches": 20129354,
    "ITLB accesses": 27441303,
    "ITLB misses": 6807,
    "DTLB misses": 20551,
    "DTLB accesses": 36867114,
    "L1I cache accesses": 31744243,
    "L1I cache misses": 271027,
    "L1D cache misses": 464135,
    "L1D cache accesses": 33441141,
    "LL cache misses": 539935,
    "LL cache accesses": 552519,
    "L2D TLB accesses": 188291,
    "L2D TLB misses": 24177,
    "L2D cache misses": 301281,
    "L2D cache accesses": 1737575,
    "instructions per cycle": 1.3731768432824245,
    "branch miss rate": 0.016971483535934636,
    "ITLB miss rate": 0.00024805673404065397,
    "DTLB miss rate": 0.0005574344658494288,
    "L2D TLB miss rate": 0.12840231344036623,
    "L1I cache miss rate": 0.008537831568388637,
    "L1D cache miss rate": 0.01387916159918108,
    "L2D cache miss rate": 0.17339165215889962,
    "LL cache miss rate": 0.9772243126480719,
    "architecture": "altra"
  },
  {
    "power_before": [
      50.88,
      50.88
    ],
    "shape": [
      11806,
      11806
    ],
    "nnz": 65460,
    "% density": 0.0004696458003979807,
    "time_s": 0.1896660327911377,
    "power": [
      25.52,
      32.28,
      33.12,
      33.12
    ],
    "power_after": [
      32.88,
      26.52
    ],
    "task clock (msec)": 42.01,
    "page faults": 3263,
    "cycles": 47084933,
    "instructions": 77895119,
    "branch mispredictions": 330923,
    "branches": 19740519,
    "ITLB accesses": 27761239,
    "ITLB misses": 6471,
    "DTLB misses": 17268,
    "DTLB accesses": 36993265,
    "L1I cache accesses": 31834980,
    "L1I cache misses": 298333,
    "L1D cache misses": 466901,
    "L1D cache accesses": 33528976,
    "LL cache misses": 525505,
    "LL cache accesses": 546521,
    "L2D TLB accesses": 184884,
    "L2D TLB misses": 22933,
    "L2D cache misses": 292367,
    "L2D cache accesses": 1706226,
    "instructions per cycle": 1.6543534000568716,
    "branch miss rate": 0.016763642333821112,
    "ITLB miss rate": 0.00023309478370183695,
    "DTLB miss rate": 0.0004667876706746485,
    "L2D TLB miss rate": 0.12403993855606758,
    "L1I cache miss rate": 0.009371232524725947,
    "L1D cache miss rate": 0.013925298523879763,
    "L2D cache miss rate": 0.1713530329510862,
    "LL cache miss rate": 0.9615458509371094,
    "architecture": "altra"
  },
  {
    "power_before": [
      30.44,
      35.52
    ],
    "shape": [
      25181,
      25181
    ],
    "nnz": 125750,
    "% density": 0.00019831796057928155,
    "time_s": 0.29622840881347656,
    "power": [
      23.84,
      29.44,
      33.0,
      33.04
    ],
    "power_after": [
      36.32,
      30.0
    ],
    "task clock (msec)": 60.77,
    "page faults": 3361,
    "cycles": 63493475,
    "instructions": 91578911,
    "branch mispredictions": 329084,
    "branches": 20406595,
    "ITLB accesses": 26859919,
    "ITLB misses": 6237,
    "DTLB misses": 16689,
    "DTLB accesses": 36348977,
    "L1I cache accesses": 30979764,
    "L1I cache misses": 292038,
    "L1D cache misses": 469219,
    "L1D cache accesses": 32411890,
    "LL cache misses": 571870,
    "LL cache accesses": 598306,
    "L2D TLB accesses": 205488,
    "L2D TLB misses": 26392,
    "L2D cache misses": 342141,
    "L2D cache accesses": 1857697,
    "instructions per cycle": 1.442335783322617,
    "branch miss rate": 0.01612635522976763,
    "ITLB miss rate": 0.00023220472109390948,
    "DTLB miss rate": 0.0004591325912693499,
    "L2D TLB miss rate": 0.12843572374055906,
    "L1I cache miss rate": 0.009426734173959492,
    "L1D cache miss rate": 0.014476755289494072,
    "L2D cache miss rate": 0.1841748142996409,
    "LL cache miss rate": 0.9558152517273769,
    "architecture": "altra"
  },
  {
    "power_before": [
      30.48,
      33.04
    ],
    "shape": [
      131828,
      131828
    ],
    "nnz": 841372,
    "% density": 4.841419648464106e-05,
    "time_s": 2.848874092102051,
    "power": [
      65.52,
      75.88,
      71.16,
      71.16,
      59.72,
      47.92,
      48.68
    ],
    "power_after": [
      68.68,
      67.88
    ],
    "task clock (msec)": 49.87,
    "page faults": 3300,
    "cycles": 51935476,
    "instructions": 83731856,
    "branch mispredictions": 326464,
    "branches": 20341367,
    "ITLB accesses": 27590154,
    "ITLB misses": 6210,
    "DTLB misses": 17536,
    "DTLB accesses": 36763243,
    "L1I cache accesses": 31663300,
    "L1I cache misses": 289727,
    "L1D cache misses": 462864,
    "L1D cache accesses": 33262254,
    "LL cache misses": 530272,
    "LL cache accesses": 551373,
    "L2D TLB accesses": 196152,
    "L2D TLB misses": 23542,
    "L2D cache misses": 301998,
    "L2D cache accesses": 1732662,
    "instructions per cycle": 1.6122285275675532,
    "branch miss rate": 0.01604926551888081,
    "ITLB miss rate": 0.000225080294948698,
    "DTLB miss rate": 0.0004769981799483794,
    "L2D TLB miss rate": 0.12001916880786329,
    "L1I cache miss rate": 0.00915024649989104,
    "L1D cache miss rate": 0.013915593332911234,
    "L2D cache miss rate": 0.17429712200071334,
    "LL cache miss rate": 0.9617300810884828,
    "architecture": "altra"
  },
  {
    "power_before": [
      20.44,
      20.2
    ],
    "shape": [
      24818,
      24818
    ],
    "nnz": 239978,
    "% density": 0.00038961697406616504,
    "time_s": 0.556269645690918,
    "power": [
      25.24,
      32.16,
      33.0,
      32.52
    ],
    "power_after": [
      34.24,
      30.28
    ],
    "task clock (msec)": 62.49,
    "page faults": 3312,
    "cycles": 76783170,
    "instructions": 77095702,
    "branch mispredictions": 323514,
    "branches": 19769937,
    "ITLB accesses": 26809325,
    "ITLB misses": 6925,
    "DTLB misses": 19003,
    "DTLB accesses": 36516965,
    "L1I cache accesses": 31104231,
    "L1I cache misses": 285499,
    "L1D cache misses": 468498,
    "L1D cache accesses": 32677465,
    "LL cache misses": 559358,
    "LL cache accesses": 571935,
    "L2D TLB accesses": 194840,
    "L2D TLB misses": 23481,
    "L2D cache misses": 313487,
    "L2D cache accesses": 1779730,
    "instructions per cycle": 1.004070319055595,
    "branch miss rate": 0.016363936819829016,
    "ITLB miss rate": 0.00025830564551699827,
    "DTLB miss rate": 0.0005203882633729282,
    "L2D TLB miss rate": 0.12051426811742968,
    "L1I cache miss rate": 0.009178783426601994,
    "L1D cache miss rate": 0.01433703624194839,
    "L2D cache miss rate": 0.1761430104566423,
    "LL cache miss rate": 0.9780097388689274,
    "architecture": "altra"
  },
  {
    "power_before": [
      16.52,
      16.64
    ],
    "shape": [
      81871,
      81871
    ],
    "nnz": 545671,
    "% density": 8.140867447881048e-05,
    "time_s": 1.3372814655303955,
    "power": [
      23.92,
      38.6,
      46.04,
      48.2,
      48.2
    ],
    "power_after": [
      45.0,
      44.08
    ],
    "task clock (msec)": 59.01,
    "page faults": 3448,
    "cycles": 73062796,
    "instructions": 88329175,
    "branch mispredictions": 331091,
    "branches": 20013316,
    "ITLB accesses": 26330936,
    "ITLB misses": 5193,
    "DTLB misses": 16837,
    "DTLB accesses": 35930477,
    "L1I cache accesses": 31853890,
    "L1I cache misses": 306147,
    "L1D cache misses": 479933,
    "L1D cache accesses": 33426019,
    "LL cache misses": 540302,
    "LL cache accesses": 553181,
    "L2D TLB accesses": 173206,
    "L2D TLB misses": 21390,
    "L2D cache misses": 300032,
    "L2D cache accesses": 1739931,
    "instructions per cycle": 1.2089487377406143,
    "branch miss rate": 0.016543535314187813,
    "ITLB miss rate": 0.0001972204861991993,
    "DTLB miss rate": 0.000468599401004334,
    "L2D TLB miss rate": 0.12349456716280037,
    "L1I cache miss rate": 0.009610976869701,
    "L1D cache miss rate": 0.014358066391334247,
    "L2D cache miss rate": 0.17243902200719455,
    "LL cache miss rate": 0.9767182893121781,
    "architecture": "altra"
  },
  {
    "power_before": [
      50.68,
      49.4
    ],
    "shape": [
      10879,
      10879
    ],
    "nnz": 39994,
    "% density": 0.0003379223282393842,
    "time_s": 0.11296772956848145,
    "power": [
      26.2,
      29.76,
      33.64,
      34.44
    ],
    "power_after": [
      36.84,
      29.44
    ],
    "task clock (msec)": 67.56,
    "page faults": 3829,
    "cycles": 47862000,
    "instructions": 84392375,
    "branch mispredictions": 331622,
    "branches": 19800140,
    "ITLB accesses": 25905045,
    "ITLB misses": 6746,
    "DTLB misses": 17547,
    "DTLB accesses": 35220079,
    "L1I cache accesses": 30359576,
    "L1I cache misses": 283204,
    "L1D cache misses": 465520,
    "L1D cache accesses": 31843274,
    "LL cache misses": 560542,
    "LL cache accesses": 575610,
    "L2D TLB accesses": 173643,
    "L2D TLB misses": 21499,
    "L2D cache misses": 313335,
    "L2D cache accesses": 1741621,
    "instructions per cycle": 1.7632438051063475,
    "branch miss rate": 0.016748467435078743,
    "ITLB miss rate": 0.0002604125953072075,
    "DTLB miss rate": 0.0004982101261044871,
    "L2D TLB miss rate": 0.12381149830399152,
    "L1I cache miss rate": 0.009328325270418797,
    "L1D cache miss rate": 0.014619099782264852,
    "L2D cache miss rate": 0.17990998041479747,
    "LL cache miss rate": 0.9738225534650197,
    "architecture": "altra"
  },
  {
    "power_before": [
      53.64,
      46.88
    ],
    "shape": [
      82144,
      82144
    ],
    "nnz": 549202,
    "% density": 8.13917555860553e-05,
    "time_s": 1.2292509078979492,
    "power": [
      40.64,
      52.44,
      54.8,
      54.96,
      46.8
    ],
    "power_after": [
      47.88,
      47.08
    ],
    "task clock (msec)": 61.26,
    "page faults": 3303,
    "cycles": 44515786,
    "instructions": 81513738,
    "branch mispredictions": 328019,
    "branches": 19893662,
    "ITLB accesses": 27248112,
    "ITLB misses": 5792,
    "DTLB misses": 16632,
    "DTLB accesses": 36929042,
    "L1I cache accesses": 31702830,
    "L1I cache misses": 295778,
    "L1D cache misses": 470423,
    "L1D cache accesses": 33155119,
    "LL cache misses": 545220,
    "LL cache accesses": 562139,
    "L2D TLB accesses": 192206,
    "L2D TLB misses": 24891,
    "L2D cache misses": 307033,
    "L2D cache accesses": 1782260,
    "instructions per cycle": 1.8311198189334452,
    "branch miss rate": 0.01648861833482443,
    "ITLB miss rate": 0.0002125651861677609,
    "DTLB miss rate": 0.0004503772396803578,
    "L2D TLB miss rate": 0.12950168048864238,
    "L1I cache miss rate": 0.009329703373484323,
    "L1D cache miss rate": 0.014188548079106578,
    "L2D cache miss rate": 0.17227172241984895,
    "LL cache miss rate": 0.9699024618466251,
    "architecture": "altra"
  },
  {
    "power_before": [
      34.04,
      43.96
    ],
    "shape": [
      32580,
      32580
    ],
    "nnz": 155598,
    "% density": 0.00014658915806621921,
    "time_s": 0.4164857864379883,
    "power": [
      23.72,
      23.72,
      29.88,
      33.32
    ],
    "power_after": [
      33.36,
      32.52
    ],
    "task clock (msec)": 61.63,
    "page faults": 3304,
    "cycles": 64734203,
    "instructions": 53597991,
    "branch mispredictions": 330777,
    "branches": 20357034,
    "ITLB accesses": 27381387,
    "ITLB misses": 6248,
    "DTLB misses": 17636,
    "DTLB accesses": 37436110,
    "L1I cache accesses": 32505993,
    "L1I cache misses": 303849,
    "L1D cache misses": 467426,
    "L1D cache accesses": 34241110,
    "LL cache misses": 550075,
    "LL cache accesses": 562829,
    "L2D TLB accesses": 199285,
    "L2D TLB misses": 24424,
    "L2D cache misses": 310155,
    "L2D cache accesses": 1783824,
    "instructions per cycle": 0.8279701999266138,
    "branch miss rate": 0.016248781625063848,
    "ITLB miss rate": 0.00022818420410916364,
    "DTLB miss rate": 0.00047109595521543235,
    "L2D TLB miss rate": 0.12255814536969667,
    "L1I cache miss rate": 0.009347476325365603,
    "L1D cache miss rate": 0.01365101773861887,
    "L2D cache miss rate": 0.17387085272986572,
    "LL cache miss rate": 0.9773394761108614,
    "architecture": "altra"
  },
  {
    "power_before": [
      16.32,
      16.2
    ],
    "shape": [
      116835,
      116835
    ],
    "nnz": 766396,
    "% density": 5.614451099680581e-05,
    "time_s": 2.2665774822235107,
    "power": [
      35.16,
      50.8,
      53.4,
      53.4,
      46.08,
      46.88
    ],
    "power_after": [
      58.4,
      57.32
    ],
    "task clock (msec)": 50.43,
    "page faults": 3285,
    "cycles": 54118679,
    "instructions": 77692421,
    "branch mispredictions": 325039,
    "branches": 19383216,
    "ITLB accesses": 26060519,
    "ITLB misses": 4749,
    "DTLB misses": 16865,
    "DTLB accesses": 34819729,
    "L1I cache accesses": 30777115,
    "L1I cache misses": 293980,
    "L1D cache misses": 461522,
    "L1D cache accesses": 32216597,
    "LL cache misses": 567700,
    "LL cache accesses": 588689,
    "L2D TLB accesses": 189417,
    "L2D TLB misses": 22360,
    "L2D cache misses": 328306,
    "L2D cache accesses": 1908607,
    "instructions per cycle": 1.4355934482436277,
    "branch miss rate": 0.0167690954896236,
    "ITLB miss rate": 0.00018222967854170517,
    "DTLB miss rate": 0.00048435184547243316,
    "L2D TLB miss rate": 0.11804642666708902,
    "L1I cache miss rate": 0.009551902444397404,
    "L1D cache miss rate": 0.014325597455249542,
    "L2D cache miss rate": 0.172013410827897,
    "LL cache miss rate": 0.9643461997761127,
    "architecture": "altra"
  },
  {
    "power_before": [
      20.16,
      20.08
    ],
    "shape": [
      31379,
      31379
    ],
    "nnz": 106762,
    "% density": 0.00010842726485909405,
    "time_s": 0.336850643157959,
    "power": [
      24.28,
      30.72,
      30.72,
      34.56
    ],
    "power_after": [
      37.32,
      32.92
    ],
    "task clock (msec)": 60.78,
    "page faults": 3300,
    "cycles": 66733059,
    "instructions": 87889334,
    "branch mispredictions": 326300,
    "branches": 19832700,
    "ITLB accesses": 27233629,
    "ITLB misses": 5868,
    "DTLB misses": 16893,
    "DTLB accesses": 36409508,
    "L1I cache accesses": 30924532,
    "L1I cache misses": 288199,
    "L1D cache misses": 462816,
    "L1D cache accesses": 32428375,
    "LL cache misses": 551997,
    "LL cache accesses": 568528,
    "L2D TLB accesses": 193991,
    "L2D TLB misses": 24353,
    "L2D cache misses": 312207,
    "L2D cache accesses": 1821196,
    "instructions per cycle": 1.3170284011707,
    "branch miss rate": 0.016452626218316214,
    "ITLB miss rate": 0.0002154688969288669,
    "DTLB miss rate": 0.00046397221297250155,
    "L2D TLB miss rate": 0.125536751704976,
    "L1I cache miss rate": 0.009319429635992551,
    "L1D cache miss rate": 0.014271945479845968,
    "L2D cache miss rate": 0.17142965391973186,
    "LL cache miss rate": 0.9709231559395491,
    "architecture": "altra"
  },
  {
    "power_before": [
      20.56,
      20.28
    ],
    "shape": [
      36682,
      36682
    ],
    "nnz": 88328,
    "% density": 6.564359899804003e-05,
    "time_s": 0.30861377716064453,
    "power": [
      23.88,
      27.6,
      39.8,
      40.12
    ],
    "power_after": [
      39.28,
      35.2
    ],
    "task clock (msec)": 65.91,
    "page faults": 3247,
    "cycles": 92293071,
    "instructions": 76208632,
    "branch mispredictions": 320083,
    "branches": 19285106,
    "ITLB accesses": 26853940,
    "ITLB misses": 6728,
    "DTLB misses": 13955,
    "DTLB accesses": 37111059,
    "L1I cache accesses": 32554796,
    "L1I cache misses": 298729,
    "L1D cache misses": 473779,
    "L1D cache accesses": 34117102,
    "LL cache misses": 535040,
    "LL cache accesses": 547502,
    "L2D TLB accesses": 179876,
    "L2D TLB misses": 21809,
    "L2D cache misses": 298620,
    "L2D cache accesses": 1722959,
    "instructions per cycle": 0.8257243059990929,
    "branch miss rate": 0.016597419791210898,
    "ITLB miss rate": 0.0002505405165871377,
    "DTLB miss rate": 0.0003760334621547717,
    "L2D TLB miss rate": 0.12124463519313304,
    "L1I cache miss rate": 0.009176190199440968,
    "L1D cache miss rate": 0.013886847716432655,
    "L2D cache miss rate": 0.17331811145825293,
    "LL cache miss rate": 0.9772384393116372,
    "architecture": "altra"
  },
  {
    "power_before": [
      34.6,
      37.16
    ],
    "shape": [
      115406,
      115406
    ],
    "nnz": 572066,
    "% density": 4.295259032005559e-05,
    "time_s": 1.0817186832427979,
    "power": [
      34.32,
      50.84,
      52.12,
      52.4,
      52.76
    ],
    "power_after": [
      49.0,
      45.08
    ],
    "task clock (msec)": 60.55,
    "page faults": 3490,
    "cycles": 49977496,
    "instructions": 78622993,
    "branch mispredictions": 327078,
    "branches": 20135808,
    "ITLB accesses": 27608093,
    "ITLB misses": 6616,
    "DTLB misses": 17185,
    "DTLB accesses": 36866957,
    "L1I cache accesses": 32639204,
    "L1I cache misses": 309643,
    "L1D cache misses": 478856,
    "L1D cache accesses": 34280618,
    "LL cache misses": 555275,
    "LL cache accesses": 578455,
    "L2D TLB accesses": 188723,
    "L2D TLB misses": 24635,
    "L2D cache misses": 319663,
    "L2D cache accesses": 1799940,
    "instructions per cycle": 1.573167911413569,
    "branch miss rate": 0.016243599462211798,
    "ITLB miss rate": 0.00023963987661154286,
    "DTLB miss rate": 0.00046613556958335347,
    "L2D TLB miss rate": 0.13053522888042263,
    "L1I cache miss rate": 0.009486842877663316,
    "L1D cache miss rate": 0.013968709665619214,
    "L2D cache miss rate": 0.17759647543807017,
    "LL cache miss rate": 0.9599277385449171,
    "architecture": "altra"
  },
  {
    "power_before": [
      16.52,
      16.24
    ],
    "shape": [
      26518,
      26518
    ],
    "nnz": 65369,
    "% density": 9.295875717624285e-05,
    "time_s": 0.1715233325958252,
    "power": [
      18.56,
      24.92,
      27.84,
      27.84
    ],
    "power_after": [
      33.2,
      27.28
    ],
    "task clock (msec)": 61.92,
    "page faults": 3281,
    "cycles": 66250810,
    "instructions": 75178179,
    "branch mispredictions": 332366,
    "branches": 19076182,
    "ITLB accesses": 27005133,
    "ITLB misses": 4791,
    "DTLB misses": 13403,
    "DTLB accesses": 36457054,
    "L1I cache accesses": 32367686,
    "L1I cache misses": 287524,
    "L1D cache misses": 467557,
    "L1D cache accesses": 34022862,
    "LL cache misses": 535707,
    "LL cache accesses": 556316,
    "L2D TLB accesses": 150149,
    "L2D TLB misses": 18418,
    "L2D cache misses": 297042,
    "L2D cache accesses": 1687364,
    "instructions per cycle": 1.1347510920998551,
    "branch miss rate": 0.017423088121092577,
    "ITLB miss rate": 0.00017741071669597036,
    "DTLB miss rate": 0.00036763804338112453,
    "L2D TLB miss rate": 0.12266481961251822,
    "L1I cache miss rate": 0.008883057009388932,
    "L1D cache miss rate": 0.013742435895016709,
    "L2D cache miss rate": 0.1760390763344483,
    "LL cache miss rate": 0.9629545078696281,
    "architecture": "altra"
  }
]