158 lines
5.2 KiB
Python
158 lines
5.2 KiB
Python
import re
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from enum import Enum
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class Stat(Enum):
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CPU = 'cpu'
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SOLVER = 'solver'
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LIN_ALG = 'linear algebra'
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INPUT_FILE = 'input file'
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MAXWELL_SIZE = 'maxwell size'
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MATRIX_COLS = 'matrix columns'
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POWER_DELTA = 'Δ watt'
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TASK_CLK = 'task clock (msec)'
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PAGE_FAULTS = 'page faults'
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CYCLES = 'cycles'
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INSTS = 'instructions'
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BR = 'branches'
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BR_MISS = 'branch mispredictions'
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ITLB = 'ITLB accesses'
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ITLB_MISS = 'ITLB misses'
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DTLB = 'DTLB accesses'
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DTLB_MISS = 'DTLB misses'
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L2D_TLB = 'L2D TLB accesses'
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L2D_TLB_MISS = 'L2D TLB misses'
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L1I_CACHE = 'L1I cache accesses'
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L1I_CACHE_MISS = 'L1I cache misses'
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L1D_CACHE = 'L1D cache accesses'
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L1D_CACHE_MISS = 'L1D cache misses'
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L2D_CACHE = 'L2D cache accesses'
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L2D_CACHE_MISS = 'L2D cache misses'
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LL_CACHE = 'LL cache accesses'
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LL_CACHE_MISS = 'LL cache misses'
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IPC = "instructions per cycle"
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BRANCH_MISS_RATE = 'branch miss rate'
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ITLB_MISS_RATE = 'ITLB miss rate'
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DTLB_MISS_RATE = 'DTLB miss rate'
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L2D_TLB_MISS_RATE = 'L2D TLB miss rate'
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L1I_CACHE_MISS_RATE = 'L1I cache miss rate'
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L1D_CACHE_MISS_RATE = 'L1D cache miss rate'
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L2D_CACHE_MISS_RATE = 'L2D cache miss rate'
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LL_CACHE_MISS_RATE = 'LL cache miss rate'
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altra_names = {
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Stat.TASK_CLK: 'task-clock:u',
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Stat.PAGE_FAULTS: 'page-faults:u',
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Stat.CYCLES: 'cycles:u',
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Stat.INSTS: 'instructions:u',
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Stat.BR: 'BR_RETIRED:u',
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Stat.BR_MISS: 'BR_MIS_PRED_RETIRED:u',
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Stat.ITLB: 'L1I_TLB:u',
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Stat.ITLB_MISS: 'ITLB_WALK:u',
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Stat.DTLB: 'L1D_TLB:u',
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Stat.DTLB_MISS: 'DTLB_WALK:u',
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Stat.L2D_TLB: 'L2D_TLB:u',
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Stat.L2D_TLB_MISS: 'L2D_TLB_REFILL:u',
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Stat.L1I_CACHE: 'L1I_CACHE:u',
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Stat.L1I_CACHE_MISS: 'L1I_CACHE_REFILL:u',
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Stat.L1D_CACHE: 'L1D_CACHE:u',
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Stat.L1D_CACHE_MISS: 'L1D_CACHE_REFILL:u',
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Stat.L2D_CACHE: 'L2D_CACHE:u',
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Stat.L2D_CACHE_MISS: 'L2D_CACHE_REFILL:u',
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Stat.LL_CACHE: 'LL_CACHE_RD:u',
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Stat.LL_CACHE_MISS: 'LL_CACHE_MISS_RD:u',
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}
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xeon_names = {
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Stat.TASK_CLK: 'task-clock:u',
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Stat.PAGE_FAULTS: 'page-faults:u',
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Stat.CYCLES: 'cycles:u',
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Stat.INSTS: 'instructions:u',
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Stat.BR: 'branches:u',
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Stat.BR_MISS: 'branch-misses:u',
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Stat.ITLB: 'iTLB-loads:u',
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Stat.ITLB_MISS: 'iTLB-load-misses:u',
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Stat.DTLB: 'dTLB-loads:u',
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Stat.DTLB_MISS: 'dTLB-load-misses:u',
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Stat.L1I_CACHE: 'L1-icache-loads:u',
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Stat.L1I_CACHE_MISS: 'L1-icache-load-misses:u',
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Stat.L1D_CACHE: 'L1-dcache-loads:u',
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Stat.L1D_CACHE_MISS: 'L1-dcache-load-misses:u',
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Stat.LL_CACHE: 'LLC-loads:u',
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Stat.LL_CACHE_MISS: 'LLC-load-misses:u',
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}
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class CPU(Enum):
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ALTRA = altra_names
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XEON = xeon_names
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def parse_output_old(filename: str, data: dict[str, str]) -> dict:
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result: dict[str, int | float] = dict()
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cpu: CPU = CPU[data['cpu'].upper()]
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with open(filename, 'r') as file:
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for line in file:
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for stat in [x for x in Stat if x in cpu.value]:
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regex = r'^\W*([\d+(,|\.)?]+)\W*.*' + cpu.value[stat]
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value = re.search(regex, line)
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if value is None:
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continue
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elif stat == Stat.TASK_CLK:
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result[stat.value] = float(value.group(1).replace(',', ''))
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else:
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result[stat.value] = int(value.group(1).replace(',', ''))
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return result | parse_power(filename, cpu)
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def parse_output(output: str, cpu: CPU) -> dict:
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result = dict()
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for line in output.split('\n'):
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for stat in [x for x in Stat if x in cpu.value]:
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regex = r'^\W*([\d+(,|\.)?]+)\W*.*' + cpu.value[stat]
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value = re.search(regex, line)
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if value is None:
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continue
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elif stat == Stat.TASK_CLK:
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result[stat.value] = float(value.group(1).replace(',', ''))
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else:
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result[stat.value] = int(value.group(1).replace(',', ''))
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return result
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def derive_stats(data: dict) -> dict:
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result = dict()
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result[Stat.IPC.value] = data[Stat.INSTS.value] / data[Stat.CYCLES.value]
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result[Stat.BRANCH_MISS_RATE.value] = (
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data[Stat.BR_MISS.value] / data[Stat.BR.value])
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result[Stat.ITLB_MISS_RATE.value] = (
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data[Stat.ITLB_MISS.value] / data[Stat.ITLB.value])
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result[Stat.DTLB_MISS_RATE.value] = (
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data[Stat.DTLB_MISS.value] / data[Stat.DTLB.value])
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result[Stat.L2D_TLB_MISS_RATE.value] = (
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data[Stat.L2D_TLB_MISS.value] / data[Stat.L2D_TLB.value]
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if Stat.L2D_TLB_MISS.value in data and Stat.L2D_TLB.value in data
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else None)
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result[Stat.L1I_CACHE_MISS_RATE.value] = (
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data[Stat.L1I_CACHE_MISS.value] / data[Stat.L1I_CACHE.value])
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result[Stat.L1D_CACHE_MISS_RATE.value] = (
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data[Stat.L1D_CACHE_MISS.value] / data[Stat.L1D_CACHE.value])
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result[Stat.L2D_CACHE_MISS_RATE.value] = (
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data[Stat.L2D_CACHE_MISS.value] / data[Stat.L2D_CACHE.value]
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if Stat.L2D_CACHE_MISS.value in data and Stat.L2D_CACHE.value in data
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else None)
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result[Stat.LL_CACHE_MISS_RATE.value] = (
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data[Stat.LL_CACHE_MISS.value] / data[Stat.LL_CACHE.value])
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return result
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