ampere_research/pytorch/output/altra_100_soc-sign-Slashdot090221_2_2.json
2024-12-02 23:32:33 -05:00

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{"power_before": [20.2, 20.32], "shape": [82144, 82144], "nnz": 549202, "% density": 8.13917555860553e-05, "time_s": 1.6952476501464844, "power": [44.68, 57.12, 64.2, 67.04, 55.68, 42.76], "power_after": [53.56, 52.52], "task clock (msec)": 61.63, "page faults": 3293, "cycles": 41677750, "instructions": 91767205, "branch mispredictions": 329386, "branches": 19813961, "ITLB accesses": 27944146, "ITLB misses": 6811, "DTLB misses": 18962, "DTLB accesses": 37689058, "L1I cache accesses": 31746573, "L1I cache misses": 290044, "L1D cache misses": 471100, "L1D cache accesses": 33271575, "LL cache misses": 550308, "LL cache accesses": 564981, "L2D TLB accesses": 168456, "L2D TLB misses": 20450, "L2D cache misses": 306309, "L2D cache accesses": 1745776, "instructions per cycle": 2.201827233955768, "branch miss rate": 0.01662393501228755, "ITLB miss rate": 0.00024373620149279208, "DTLB miss rate": 0.0005031168462740565, "L2D TLB miss rate": 0.12139668518782352, "L1I cache miss rate": 0.009136230231842662, "L1D cache miss rate": 0.014159233519904002, "L2D cache miss rate": 0.17545721787904062, "LL cache miss rate": 0.9740292151417481}