3377 lines
104 KiB
JSON
3377 lines
104 KiB
JSON
|
[
|
||
|
{
|
||
|
"cpu": "altra",
|
||
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|
||
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|
||
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|
||
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||
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||
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|
||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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|
||
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|
||
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||
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||
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||
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||
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|
||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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|
||
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|
||
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|
||
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|
||
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||
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||
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||
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||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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|
||
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|
||
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||
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||
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||
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||
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||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
"cpu": "xeon",
|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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||
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||
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||
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|
||
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||
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||
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||
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|
||
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|
||
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell24",
|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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||
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||
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||
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||
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||
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||
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||
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"L1D cache misses": 379049,
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||
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||
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||
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||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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||
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|
||
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|
||
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|
||
|
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|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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||
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||
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|
||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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|
||
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||
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|
||
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|
||
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||
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||
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|
||
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|
||
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||
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||
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|
||
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||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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|
||
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||
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||
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||
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|
||
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|
||
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|
||
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||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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||
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||
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|
||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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||
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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||
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||
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|
||
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|
||
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
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||
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||
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||
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||
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||
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||
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||
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||
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||
|
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|
||
|
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|
||
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|
||
|
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||
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|
||
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|
||
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|
||
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||
|
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|
||
|
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|
||
|
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|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
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|
||
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|
||
|
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||
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|
||
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||
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|
||
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||
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||
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|
||
|
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|
||
|
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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||
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||
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|
||
|
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||
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|
||
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||
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||
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|
||
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||
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|
||
|
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|
||
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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||
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell18",
|
||
|
"maxwell size": 18,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell40",
|
||
|
"maxwell size": 40,
|
||
|
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|
||
|
"task clock (msec)": 36.17,
|
||
|
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|
||
|
"cycles": 33198359,
|
||
|
"instructions": 75365745,
|
||
|
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|
||
|
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|
||
|
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||
|
"ITLB misses": 4902,
|
||
|
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|
||
|
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|
||
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|
||
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"L1I cache misses": 232631,
|
||
|
"L1D cache misses": 382824,
|
||
|
"L1D cache accesses": 27869172,
|
||
|
"LL cache misses": 444027,
|
||
|
"LL cache accesses": 472773,
|
||
|
"L2D TLB accesses": 160036,
|
||
|
"L2D TLB misses": 21546,
|
||
|
"L2D cache misses": 251471,
|
||
|
"L2D cache accesses": 1491358,
|
||
|
"\u0394 watt": 17.956,
|
||
|
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|
||
|
"ITLB miss rate": 0.00021738699501593084,
|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013736468381622532,
|
||
|
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||
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|
||
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|
||
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|
||
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"cpu": "altra",
|
||
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"solver": "MueLu",
|
||
|
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|
||
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"input file": "maxwell32",
|
||
|
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|
||
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"matrix columns": 104544,
|
||
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|
||
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"page faults": 2775,
|
||
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"cycles": 34850201,
|
||
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"instructions": 75677644,
|
||
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"branch mispredictions": 311509,
|
||
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|
||
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"ITLB accesses": 22461744,
|
||
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"ITLB misses": 5685,
|
||
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"DTLB misses": 12876,
|
||
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|
||
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"L1I cache accesses": 26404687,
|
||
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"L1I cache misses": 225017,
|
||
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"L1D cache misses": 376676,
|
||
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"L1D cache accesses": 27688364,
|
||
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"LL cache misses": 470244,
|
||
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"LL cache accesses": 497265,
|
||
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"L2D TLB accesses": 138358,
|
||
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"L2D TLB misses": 19781,
|
||
|
"L2D cache misses": 257258,
|
||
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"L2D cache accesses": 1475249,
|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
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"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell20",
|
||
|
"maxwell size": 20,
|
||
|
"matrix columns": 26460,
|
||
|
"task clock (msec)": 34.98,
|
||
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"page faults": 2770,
|
||
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"cycles": 35843362,
|
||
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|
||
|
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|
||
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|
||
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|
||
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|
||
|
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|
||
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|
||
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"L1I cache accesses": 26628016,
|
||
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"L1I cache misses": 240445,
|
||
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"L1D cache misses": 377989,
|
||
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"L1D cache accesses": 27940782,
|
||
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"LL cache misses": 470547,
|
||
|
"LL cache accesses": 499243,
|
||
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"L2D TLB accesses": 137928,
|
||
|
"L2D TLB misses": 17380,
|
||
|
"L2D cache misses": 260705,
|
||
|
"L2D cache accesses": 1463776,
|
||
|
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|
||
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"branch miss rate": 0.018786710591459234,
|
||
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|
||
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|
||
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|
||
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"L1D cache miss rate": 0.013528218358383814,
|
||
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"L2D cache miss rate": 0.17810443674441992,
|
||
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"LL cache miss rate": 0.9425209767588129
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell14",
|
||
|
"maxwell size": 14,
|
||
|
"matrix columns": 9450,
|
||
|
"task clock (msec)": 35.41,
|
||
|
"page faults": 2765,
|
||
|
"cycles": 37140362,
|
||
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"instructions": 73876599,
|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
"DTLB misses": 12331,
|
||
|
"DTLB accesses": 30733042,
|
||
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"L1I cache accesses": 26630439,
|
||
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"L1I cache misses": 237304,
|
||
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"L1D cache misses": 387464,
|
||
|
"L1D cache accesses": 27899970,
|
||
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"LL cache misses": 465815,
|
||
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"LL cache accesses": 485283,
|
||
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"L2D TLB accesses": 135965,
|
||
|
"L2D TLB misses": 17774,
|
||
|
"L2D cache misses": 248162,
|
||
|
"L2D cache accesses": 1468216,
|
||
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|
||
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"branch miss rate": 0.018873580615870408,
|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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"LL cache miss rate": 0.9598832021727528
|
||
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell50",
|
||
|
"maxwell size": 50,
|
||
|
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|
||
|
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|
||
|
"page faults": 2748,
|
||
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|
||
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|
||
|
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|
||
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||
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||
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|
||
|
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|
||
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|
||
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|
||
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"L1I cache misses": 227711,
|
||
|
"L1D cache misses": 376129,
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||
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"L1D cache accesses": 28040627,
|
||
|
"LL cache misses": 459818,
|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
"LL cache miss rate": 0.9599500628389861
|
||
|
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell10",
|
||
|
"maxwell size": 10,
|
||
|
"matrix columns": 3630,
|
||
|
"task clock (msec)": 26.61,
|
||
|
"page faults": 2740,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache accesses": 18106537,
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||
|
"L1D cache misses": 582639,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache miss rate": null,
|
||
|
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|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell46",
|
||
|
"maxwell size": 46,
|
||
|
"matrix columns": 304842,
|
||
|
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|
||
|
"page faults": 2814,
|
||
|
"cycles": 36640121,
|
||
|
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|
||
|
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|
||
|
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||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
"L1D cache misses": 380204,
|
||
|
"L1D cache accesses": 27687572,
|
||
|
"LL cache misses": 462660,
|
||
|
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|
||
|
"L2D TLB accesses": 136834,
|
||
|
"L2D TLB misses": 17359,
|
||
|
"L2D cache misses": 250884,
|
||
|
"L2D cache accesses": 1453835,
|
||
|
"\u0394 watt": 13.985333333333333,
|
||
|
"branch miss rate": 0.018468010434645035,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache miss rate": 0.17256703821272704,
|
||
|
"LL cache miss rate": 0.955435321328267
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell38",
|
||
|
"maxwell size": 38,
|
||
|
"matrix columns": 173394,
|
||
|
"task clock (msec)": 35.51,
|
||
|
"page faults": 2769,
|
||
|
"cycles": 34057119,
|
||
|
"instructions": 74858259,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 380936,
|
||
|
"L1D cache accesses": 27654401,
|
||
|
"LL cache misses": 464375,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache misses": 253615,
|
||
|
"L2D cache accesses": 1460608,
|
||
|
"\u0394 watt": 11.418666666666667,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013774878002239137,
|
||
|
"L2D cache miss rate": 0.1736365951713259,
|
||
|
"LL cache miss rate": 0.9515491168394737
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell50",
|
||
|
"maxwell size": 50,
|
||
|
"matrix columns": 390150,
|
||
|
"task clock (msec)": 32.64,
|
||
|
"page faults": 2756,
|
||
|
"cycles": 35412935,
|
||
|
"instructions": 74655974,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 385092,
|
||
|
"L1D cache accesses": 27790301,
|
||
|
"LL cache misses": 469441,
|
||
|
"LL cache accesses": 501026,
|
||
|
"L2D TLB accesses": 138495,
|
||
|
"L2D TLB misses": 19115,
|
||
|
"L2D cache misses": 262301,
|
||
|
"L2D cache accesses": 1493319,
|
||
|
"\u0394 watt": 18.674666666666667,
|
||
|
"branch miss rate": 0.018849356674418706,
|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": 0.00922836944918897,
|
||
|
"L1D cache miss rate": 0.013857064736362517,
|
||
|
"L2D cache miss rate": 0.17564967699466758,
|
||
|
"LL cache miss rate": 0.9369593593945225
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell12",
|
||
|
"maxwell size": 12,
|
||
|
"matrix columns": 6084,
|
||
|
"task clock (msec)": 31.26,
|
||
|
"page faults": 3259,
|
||
|
"cycles": 50199983,
|
||
|
"instructions": 79261227,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 15360,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 578648,
|
||
|
"LL cache accesses": 70731,
|
||
|
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|
||
|
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|
||
|
"ITLB miss rate": 1.6733849003159385,
|
||
|
"DTLB miss rate": 0.0008552197235490055,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.03246611230861816,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.34440344403444034
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell4",
|
||
|
"maxwell size": 4,
|
||
|
"matrix columns": 300,
|
||
|
"task clock (msec)": 34.07,
|
||
|
"page faults": 2759,
|
||
|
"cycles": 35815677,
|
||
|
"instructions": 75698838,
|
||
|
"branch mispredictions": 308569,
|
||
|
"branches": 16734313,
|
||
|
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|
||
|
"ITLB misses": 4963,
|
||
|
"DTLB misses": 12200,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 386049,
|
||
|
"L1D cache accesses": 27683683,
|
||
|
"LL cache misses": 472377,
|
||
|
"LL cache accesses": 499919,
|
||
|
"L2D TLB accesses": 134780,
|
||
|
"L2D TLB misses": 17580,
|
||
|
"L2D cache misses": 263006,
|
||
|
"L2D cache accesses": 1483782,
|
||
|
"\u0394 watt": 3.6693333333333342,
|
||
|
"branch miss rate": 0.018439298942239217,
|
||
|
"ITLB miss rate": 0.00021705105506143117,
|
||
|
"DTLB miss rate": 0.000397820283969336,
|
||
|
"L1I cache miss rate": 0.008754606084714888,
|
||
|
"L1D cache miss rate": 0.013945001465303588,
|
||
|
"L2D cache miss rate": 0.17725380143444253,
|
||
|
"LL cache miss rate": 0.9449070749461412
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell34",
|
||
|
"maxwell size": 34,
|
||
|
"matrix columns": 124950,
|
||
|
"task clock (msec)": 35.39,
|
||
|
"page faults": 2757,
|
||
|
"cycles": 35019558,
|
||
|
"instructions": 73884050,
|
||
|
"branch mispredictions": 311820,
|
||
|
"branches": 17013235,
|
||
|
"ITLB accesses": 22753628,
|
||
|
"ITLB misses": 5573,
|
||
|
"DTLB misses": 12737,
|
||
|
"DTLB accesses": 30471484,
|
||
|
"L1I cache accesses": 26688842,
|
||
|
"L1I cache misses": 234773,
|
||
|
"L1D cache misses": 379425,
|
||
|
"L1D cache accesses": 27966418,
|
||
|
"LL cache misses": 444727,
|
||
|
"LL cache accesses": 464326,
|
||
|
"L2D TLB accesses": 158917,
|
||
|
"L2D TLB misses": 21453,
|
||
|
"L2D cache misses": 244029,
|
||
|
"L2D cache accesses": 1473015,
|
||
|
"\u0394 watt": 12.477333333333334,
|
||
|
"branch miss rate": 0.01832808398872995,
|
||
|
"ITLB miss rate": 0.00024492797368402087,
|
||
|
"DTLB miss rate": 0.0004179973643554741,
|
||
|
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|
||
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"L1D cache miss rate": 0.013567164733073789,
|
||
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|
||
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"LL cache miss rate": 0.9577904317225397
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell42",
|
||
|
"maxwell size": 42,
|
||
|
"matrix columns": 232974,
|
||
|
"task clock (msec)": 38.94,
|
||
|
"page faults": 2771,
|
||
|
"cycles": 38604757,
|
||
|
"instructions": 77657485,
|
||
|
"branch mispredictions": 311614,
|
||
|
"branches": 16694225,
|
||
|
"ITLB accesses": 22898357,
|
||
|
"ITLB misses": 5552,
|
||
|
"DTLB misses": 13048,
|
||
|
"DTLB accesses": 30770993,
|
||
|
"L1I cache accesses": 26383983,
|
||
|
"L1I cache misses": 223528,
|
||
|
"L1D cache misses": 375899,
|
||
|
"L1D cache accesses": 27687659,
|
||
|
"LL cache misses": 458067,
|
||
|
"LL cache accesses": 477325,
|
||
|
"L2D TLB accesses": 134565,
|
||
|
"L2D TLB misses": 17564,
|
||
|
"L2D cache misses": 245351,
|
||
|
"L2D cache accesses": 1438299,
|
||
|
"\u0394 watt": 12.877333333333336,
|
||
|
"branch miss rate": 0.01866597580899982,
|
||
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"ITLB miss rate": 0.00024246281075974142,
|
||
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"DTLB miss rate": 0.0004240357144145462,
|
||
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"L1I cache miss rate": 0.008472109764473393,
|
||
|
"L1D cache miss rate": 0.013576409619895998,
|
||
|
"L2D cache miss rate": 0.17058414140592465,
|
||
|
"LL cache miss rate": 0.9596543235740848
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell34",
|
||
|
"maxwell size": 34,
|
||
|
"matrix columns": 124950,
|
||
|
"task clock (msec)": 31.69,
|
||
|
"page faults": 2762,
|
||
|
"cycles": 31887058,
|
||
|
"instructions": 74429157,
|
||
|
"branch mispredictions": 319093,
|
||
|
"branches": 16928644,
|
||
|
"ITLB accesses": 22662945,
|
||
|
"ITLB misses": 5028,
|
||
|
"DTLB misses": 12059,
|
||
|
"DTLB accesses": 30464264,
|
||
|
"L1I cache accesses": 26360446,
|
||
|
"L1I cache misses": 225534,
|
||
|
"L1D cache misses": 377754,
|
||
|
"L1D cache accesses": 27615755,
|
||
|
"LL cache misses": 454234,
|
||
|
"LL cache accesses": 483749,
|
||
|
"L2D TLB accesses": 155422,
|
||
|
"L2D TLB misses": 22005,
|
||
|
"L2D cache misses": 258239,
|
||
|
"L2D cache accesses": 1497679,
|
||
|
"\u0394 watt": 10.676000000000002,
|
||
|
"branch miss rate": 0.01884929472201081,
|
||
|
"ITLB miss rate": 0.0002218599568590931,
|
||
|
"DTLB miss rate": 0.000395840844866628,
|
||
|
"L1I cache miss rate": 0.00855577329761416,
|
||
|
"L1D cache miss rate": 0.013678930740803574,
|
||
|
"L2D cache miss rate": 0.17242613403806822,
|
||
|
"LL cache miss rate": 0.9389869539781994
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell22",
|
||
|
"maxwell size": 22,
|
||
|
"matrix columns": 34914,
|
||
|
"task clock (msec)": 35.66,
|
||
|
"page faults": 2783,
|
||
|
"cycles": 28797561,
|
||
|
"instructions": 72611886,
|
||
|
"branch mispredictions": 314831,
|
||
|
"branches": 16822795,
|
||
|
"ITLB accesses": 22365064,
|
||
|
"ITLB misses": 5315,
|
||
|
"DTLB misses": 12146,
|
||
|
"DTLB accesses": 29931897,
|
||
|
"L1I cache accesses": 26478185,
|
||
|
"L1I cache misses": 232023,
|
||
|
"L1D cache misses": 378229,
|
||
|
"L1D cache accesses": 27831494,
|
||
|
"LL cache misses": 448786,
|
||
|
"LL cache accesses": 468750,
|
||
|
"L2D TLB accesses": 130012,
|
||
|
"L2D TLB misses": 16264,
|
||
|
"L2D cache misses": 238552,
|
||
|
"L2D cache accesses": 1420866,
|
||
|
"\u0394 watt": 13.818666666666665,
|
||
|
"branch miss rate": 0.018714547731218268,
|
||
|
"ITLB miss rate": 0.00023764743083230168,
|
||
|
"DTLB miss rate": 0.0004057878456550883,
|
||
|
"L1I cache miss rate": 0.008762798507526101,
|
||
|
"L1D cache miss rate": 0.013589963945162268,
|
||
|
"L2D cache miss rate": 0.16789197573873962,
|
||
|
"LL cache miss rate": 0.9574101333333334
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell12",
|
||
|
"maxwell size": 12,
|
||
|
"matrix columns": 6084,
|
||
|
"task clock (msec)": 38.24,
|
||
|
"page faults": 2791,
|
||
|
"cycles": 38107904,
|
||
|
"instructions": 76348269,
|
||
|
"branch mispredictions": 316120,
|
||
|
"branches": 17064379,
|
||
|
"ITLB accesses": 22594643,
|
||
|
"ITLB misses": 5428,
|
||
|
"DTLB misses": 12324,
|
||
|
"DTLB accesses": 30768538,
|
||
|
"L1I cache accesses": 26740932,
|
||
|
"L1I cache misses": 233141,
|
||
|
"L1D cache misses": 388857,
|
||
|
"L1D cache accesses": 28098450,
|
||
|
"LL cache misses": 466769,
|
||
|
"LL cache accesses": 489164,
|
||
|
"L2D TLB accesses": 133866,
|
||
|
"L2D TLB misses": 16446,
|
||
|
"L2D cache misses": 250317,
|
||
|
"L2D cache accesses": 1469531,
|
||
|
"\u0394 watt": 1.4426666666666712,
|
||
|
"branch miss rate": 0.01852513941468365,
|
||
|
"ITLB miss rate": 0.00024023393509691655,
|
||
|
"DTLB miss rate": 0.00040053901813599335,
|
||
|
"L1I cache miss rate": 0.008718506894224928,
|
||
|
"L1D cache miss rate": 0.013839090768351991,
|
||
|
"L2D cache miss rate": 0.17033801940891347,
|
||
|
"LL cache miss rate": 0.9542178083423964
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell24",
|
||
|
"maxwell size": 24,
|
||
|
"matrix columns": 45000,
|
||
|
"task clock (msec)": 31.53,
|
||
|
"page faults": 2757,
|
||
|
"cycles": 38154360,
|
||
|
"instructions": 76003480,
|
||
|
"branch mispredictions": 314535,
|
||
|
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|
||
|
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|
||
|
"ITLB misses": 5040,
|
||
|
"DTLB misses": 11917,
|
||
|
"DTLB accesses": 30403638,
|
||
|
"L1I cache accesses": 26635517,
|
||
|
"L1I cache misses": 238993,
|
||
|
"L1D cache misses": 384206,
|
||
|
"L1D cache accesses": 27836639,
|
||
|
"LL cache misses": 475418,
|
||
|
"LL cache accesses": 501247,
|
||
|
"L2D TLB accesses": 133593,
|
||
|
"L2D TLB misses": 17654,
|
||
|
"L2D cache misses": 262844,
|
||
|
"L2D cache accesses": 1466034,
|
||
|
"\u0394 watt": 6.961333333333332,
|
||
|
"branch miss rate": 0.01870062536375209,
|
||
|
"ITLB miss rate": 0.00022247374114624032,
|
||
|
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|
||
|
"L1I cache miss rate": 0.008972718644807984,
|
||
|
"L1D cache miss rate": 0.013802169148365935,
|
||
|
"L2D cache miss rate": 0.17928915700454423,
|
||
|
"LL cache miss rate": 0.9484705145367454
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell4",
|
||
|
"maxwell size": 4,
|
||
|
"matrix columns": 300,
|
||
|
"task clock (msec)": 28.84,
|
||
|
"page faults": 3238,
|
||
|
"cycles": 46524233,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 13621,
|
||
|
"DTLB accesses": 17783780,
|
||
|
"DTLB misses": 12598,
|
||
|
"L1D cache accesses": 17494763,
|
||
|
"L1D cache misses": 576538,
|
||
|
"LL cache accesses": 67358,
|
||
|
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|
||
|
"branch miss rate": 0.01752511235384501,
|
||
|
"ITLB miss rate": 2.257000828500414,
|
||
|
"DTLB miss rate": 0.0007083983270148416,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.032954890557820075,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.16400427566139136
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell14",
|
||
|
"maxwell size": 14,
|
||
|
"matrix columns": 9450,
|
||
|
"task clock (msec)": 27.25,
|
||
|
"page faults": 2736,
|
||
|
"cycles": 45435644,
|
||
|
"instructions": 78271647,
|
||
|
"branches": 16994482,
|
||
|
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|
||
|
"ITLB accesses": 7616,
|
||
|
"ITLB misses": 14515,
|
||
|
"DTLB accesses": 17745451,
|
||
|
"DTLB misses": 14184,
|
||
|
"L1D cache accesses": 17720302,
|
||
|
"L1D cache misses": 572377,
|
||
|
"LL cache accesses": 63704,
|
||
|
"LL cache misses": 11538,
|
||
|
"branch miss rate": 0.017177693324221355,
|
||
|
"ITLB miss rate": 1.9058560924369747,
|
||
|
"DTLB miss rate": 0.0007993034383854205,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.03230063460543731,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.1811189250282557
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell28",
|
||
|
"maxwell size": 28,
|
||
|
"matrix columns": 70644,
|
||
|
"task clock (msec)": 37.43,
|
||
|
"page faults": 2760,
|
||
|
"cycles": 38247751,
|
||
|
"instructions": 74492341,
|
||
|
"branch mispredictions": 315870,
|
||
|
"branches": 16808953,
|
||
|
"ITLB accesses": 22562493,
|
||
|
"ITLB misses": 4714,
|
||
|
"DTLB misses": 12202,
|
||
|
"DTLB accesses": 30307579,
|
||
|
"L1I cache accesses": 26528925,
|
||
|
"L1I cache misses": 229763,
|
||
|
"L1D cache misses": 371071,
|
||
|
"L1D cache accesses": 27793339,
|
||
|
"LL cache misses": 473991,
|
||
|
"LL cache accesses": 495456,
|
||
|
"L2D TLB accesses": 134781,
|
||
|
"L2D TLB misses": 17650,
|
||
|
"L2D cache misses": 257771,
|
||
|
"L2D cache accesses": 1472049,
|
||
|
"\u0394 watt": 18.604000000000006,
|
||
|
"branch miss rate": 0.018791771266181777,
|
||
|
"ITLB miss rate": 0.00020893081274307764,
|
||
|
"DTLB miss rate": 0.0004026055660862915,
|
||
|
"L1I cache miss rate": 0.008660848488960635,
|
||
|
"L1D cache miss rate": 0.01335107667344323,
|
||
|
"L2D cache miss rate": 0.1751103393976695,
|
||
|
"LL cache miss rate": 0.9566762739779112
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell8",
|
||
|
"maxwell size": 8,
|
||
|
"matrix columns": 1944,
|
||
|
"task clock (msec)": 35.44,
|
||
|
"page faults": 2764,
|
||
|
"cycles": 36127271,
|
||
|
"instructions": 76768925,
|
||
|
"branch mispredictions": 316239,
|
||
|
"branches": 16877036,
|
||
|
"ITLB accesses": 22436874,
|
||
|
"ITLB misses": 5008,
|
||
|
"DTLB misses": 11966,
|
||
|
"DTLB accesses": 30170027,
|
||
|
"L1I cache accesses": 26578511,
|
||
|
"L1I cache misses": 230855,
|
||
|
"L1D cache misses": 365266,
|
||
|
"L1D cache accesses": 27855340,
|
||
|
"LL cache misses": 459831,
|
||
|
"LL cache accesses": 478879,
|
||
|
"L2D TLB accesses": 134853,
|
||
|
"L2D TLB misses": 17671,
|
||
|
"L2D cache misses": 246499,
|
||
|
"L2D cache accesses": 1431433,
|
||
|
"\u0394 watt": 2.924000000000003,
|
||
|
"branch miss rate": 0.01873782813522469,
|
||
|
"ITLB miss rate": 0.0002232039989171397,
|
||
|
"DTLB miss rate": 0.00039661880315851225,
|
||
|
"L1I cache miss rate": 0.008685776264893093,
|
||
|
"L1D cache miss rate": 0.013112961464480419,
|
||
|
"L2D cache miss rate": 0.1722043574515887,
|
||
|
"LL cache miss rate": 0.9602237726022649
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell20",
|
||
|
"maxwell size": 20,
|
||
|
"matrix columns": 26460,
|
||
|
"task clock (msec)": 34.7,
|
||
|
"page faults": 2768,
|
||
|
"cycles": 26451940,
|
||
|
"instructions": 72629827,
|
||
|
"branch mispredictions": 318871,
|
||
|
"branches": 16901235,
|
||
|
"ITLB accesses": 22500323,
|
||
|
"ITLB misses": 5270,
|
||
|
"DTLB misses": 12429,
|
||
|
"DTLB accesses": 30168626,
|
||
|
"L1I cache accesses": 26444828,
|
||
|
"L1I cache misses": 226916,
|
||
|
"L1D cache misses": 373966,
|
||
|
"L1D cache accesses": 27747568,
|
||
|
"LL cache misses": 463884,
|
||
|
"LL cache accesses": 483483,
|
||
|
"L2D TLB accesses": 134714,
|
||
|
"L2D TLB misses": 17910,
|
||
|
"L2D cache misses": 244944,
|
||
|
"L2D cache accesses": 1458075,
|
||
|
"\u0394 watt": 5.628,
|
||
|
"branch miss rate": 0.018866727786460574,
|
||
|
"ITLB miss rate": 0.00023421885988036706,
|
||
|
"DTLB miss rate": 0.00041198429123023367,
|
||
|
"L1I cache miss rate": 0.008580732686179695,
|
||
|
"L1D cache miss rate": 0.013477433409659543,
|
||
|
"L2D cache miss rate": 0.16799135846921454,
|
||
|
"LL cache miss rate": 0.9594628973510961
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell48",
|
||
|
"maxwell size": 48,
|
||
|
"matrix columns": 345744,
|
||
|
"task clock (msec)": 35.09,
|
||
|
"page faults": 2777,
|
||
|
"cycles": 35498307,
|
||
|
"instructions": 74874275,
|
||
|
"branch mispredictions": 309679,
|
||
|
"branches": 16861431,
|
||
|
"ITLB accesses": 22803677,
|
||
|
"ITLB misses": 5037,
|
||
|
"DTLB misses": 12129,
|
||
|
"DTLB accesses": 30733658,
|
||
|
"L1I cache accesses": 26477891,
|
||
|
"L1I cache misses": 229830,
|
||
|
"L1D cache misses": 377265,
|
||
|
"L1D cache accesses": 27773004,
|
||
|
"LL cache misses": 470738,
|
||
|
"LL cache accesses": 496153,
|
||
|
"L2D TLB accesses": 133031,
|
||
|
"L2D TLB misses": 17983,
|
||
|
"L2D cache misses": 258141,
|
||
|
"L2D cache accesses": 1471401,
|
||
|
"\u0394 watt": 14.819999999999997,
|
||
|
"branch miss rate": 0.01836611613806681,
|
||
|
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|
||
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||
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||
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||
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|
||
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|
||
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|
||
|
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|
||
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"cpu": "xeon",
|
||
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"solver": "CG",
|
||
|
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|
||
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"input file": "maxwell20",
|
||
|
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|
||
|
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|
||
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|
||
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"page faults": 3257,
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||
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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|
||
|
"DTLB misses": 14791,
|
||
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|
||
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"L1D cache misses": 574506,
|
||
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|
||
|
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|
||
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|
||
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|
||
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||
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|
||
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|
||
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"L2D cache miss rate": null,
|
||
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|
||
|
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|
||
|
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|
||
|
"cpu": "xeon",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell12",
|
||
|
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|
||
|
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|
||
|
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|
||
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"page faults": 2757,
|
||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 14373,
|
||
|
"DTLB accesses": 17813443,
|
||
|
"DTLB misses": 14801,
|
||
|
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|
||
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"L1D cache misses": 577762,
|
||
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|
||
|
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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"L2D cache miss rate": null,
|
||
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"LL cache miss rate": 0.1896169079486479
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell12",
|
||
|
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|
||
|
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|
||
|
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|
||
|
"page faults": 2759,
|
||
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"cycles": 30945071,
|
||
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"instructions": 69398421,
|
||
|
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|
||
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|
||
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||
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|
||
|
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|
||
|
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|
||
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|
||
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"L1I cache misses": 230256,
|
||
|
"L1D cache misses": 382347,
|
||
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"L1D cache accesses": 27731498,
|
||
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"LL cache misses": 459487,
|
||
|
"LL cache accesses": 479612,
|
||
|
"L2D TLB accesses": 136168,
|
||
|
"L2D TLB misses": 16861,
|
||
|
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|
||
|
"L2D cache accesses": 1432491,
|
||
|
"\u0394 watt": 11.930666666666667,
|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
"LL cache miss rate": 0.9580389981902038
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell18",
|
||
|
"maxwell size": 18,
|
||
|
"matrix columns": 19494,
|
||
|
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|
||
|
"page faults": 2772,
|
||
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"cycles": 35361566,
|
||
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"instructions": 75377352,
|
||
|
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|
||
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||
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||
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|
||
|
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|
||
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|
||
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|
||
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"L1I cache misses": 234493,
|
||
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"L1D cache misses": 375748,
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||
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"L1D cache accesses": 27804002,
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||
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"LL cache misses": 474052,
|
||
|
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|
||
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"L2D TLB accesses": 140197,
|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
|
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|
||
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|
||
|
"L1D cache miss rate": 0.013514169650829402,
|
||
|
"L2D cache miss rate": 0.18078765420478518,
|
||
|
"LL cache miss rate": 0.9438641621834718
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell36",
|
||
|
"maxwell size": 36,
|
||
|
"matrix columns": 147852,
|
||
|
"task clock (msec)": 33.29,
|
||
|
"page faults": 2784,
|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
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|
||
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|
||
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||
|
"L1D cache misses": 392627,
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||
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"L1D cache accesses": 28111869,
|
||
|
"LL cache misses": 471324,
|
||
|
"LL cache accesses": 510684,
|
||
|
"L2D TLB accesses": 136615,
|
||
|
"L2D TLB misses": 18298,
|
||
|
"L2D cache misses": 272960,
|
||
|
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|
||
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|
||
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|
||
|
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||
|
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|
||
|
"L1I cache miss rate": 0.009014706996453542,
|
||
|
"L1D cache miss rate": 0.013966591833506339,
|
||
|
"L2D cache miss rate": 0.1818358654190765,
|
||
|
"LL cache miss rate": 0.9229268980426252
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
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|
||
|
"input file": "maxwell46",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
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|
||
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|
||
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||
|
"L1D cache misses": 373324,
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||
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"L1D cache accesses": 27436569,
|
||
|
"LL cache misses": 465023,
|
||
|
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|
||
|
"L2D TLB accesses": 135926,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"\u0394 watt": 14.650666666666666,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013606803387114475,
|
||
|
"L2D cache miss rate": 0.17433128901097406,
|
||
|
"LL cache miss rate": 0.9445044744955783
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell10",
|
||
|
"maxwell size": 10,
|
||
|
"matrix columns": 3630,
|
||
|
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|
||
|
"page faults": 2771,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache misses": 246882,
|
||
|
"L1D cache misses": 387738,
|
||
|
"L1D cache accesses": 27767626,
|
||
|
"LL cache misses": 459949,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache misses": 245227,
|
||
|
"L2D cache accesses": 1451665,
|
||
|
"\u0394 watt": 3.324000000000005,
|
||
|
"branch miss rate": 0.018576837521296508,
|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": 0.009245560094286872,
|
||
|
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|
||
|
"L2D cache miss rate": 0.16892809291399874,
|
||
|
"LL cache miss rate": 0.9523404290562295
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell16",
|
||
|
"maxwell size": 16,
|
||
|
"matrix columns": 13872,
|
||
|
"task clock (msec)": 33.37,
|
||
|
"page faults": 2779,
|
||
|
"cycles": 36802889,
|
||
|
"instructions": 75056728,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache accesses": 26480842,
|
||
|
"L1I cache misses": 225755,
|
||
|
"L1D cache misses": 369823,
|
||
|
"L1D cache accesses": 27799943,
|
||
|
"LL cache misses": 457189,
|
||
|
"LL cache accesses": 485992,
|
||
|
"L2D TLB accesses": 131135,
|
||
|
"L2D TLB misses": 17503,
|
||
|
"L2D cache misses": 250990,
|
||
|
"L2D cache accesses": 1464593,
|
||
|
"\u0394 watt": 6.472000000000001,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013303012887472467,
|
||
|
"L2D cache miss rate": 0.17137184187006219,
|
||
|
"LL cache miss rate": 0.9407335923225074
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell30",
|
||
|
"maxwell size": 30,
|
||
|
"matrix columns": 86490,
|
||
|
"task clock (msec)": 34.81,
|
||
|
"page faults": 2765,
|
||
|
"cycles": 36773990,
|
||
|
"instructions": 74420116,
|
||
|
"branch mispredictions": 314951,
|
||
|
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|
||
|
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|
||
|
"ITLB misses": 5607,
|
||
|
"DTLB misses": 12638,
|
||
|
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|
||
|
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|
||
|
"L1I cache misses": 236758,
|
||
|
"L1D cache misses": 383812,
|
||
|
"L1D cache accesses": 28459501,
|
||
|
"LL cache misses": 457211,
|
||
|
"LL cache accesses": 476767,
|
||
|
"L2D TLB accesses": 134166,
|
||
|
"L2D TLB misses": 16622,
|
||
|
"L2D cache misses": 241461,
|
||
|
"L2D cache accesses": 1434082,
|
||
|
"\u0394 watt": 8.020000000000003,
|
||
|
"branch miss rate": 0.01848056281658022,
|
||
|
"ITLB miss rate": 0.00024934188107126026,
|
||
|
"DTLB miss rate": 0.0004185841006933565,
|
||
|
"L1I cache miss rate": 0.008754598319876482,
|
||
|
"L1D cache miss rate": 0.013486251919877302,
|
||
|
"L2D cache miss rate": 0.16837321715215728,
|
||
|
"LL cache miss rate": 0.9589820604194502
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell32",
|
||
|
"maxwell size": 32,
|
||
|
"matrix columns": 104544,
|
||
|
"task clock (msec)": 37.31,
|
||
|
"page faults": 2777,
|
||
|
"cycles": 34048763,
|
||
|
"instructions": 74343582,
|
||
|
"branch mispredictions": 317436,
|
||
|
"branches": 16874761,
|
||
|
"ITLB accesses": 22591179,
|
||
|
"ITLB misses": 4795,
|
||
|
"DTLB misses": 11739,
|
||
|
"DTLB accesses": 30359421,
|
||
|
"L1I cache accesses": 26705866,
|
||
|
"L1I cache misses": 229557,
|
||
|
"L1D cache misses": 377734,
|
||
|
"L1D cache accesses": 28114986,
|
||
|
"LL cache misses": 463225,
|
||
|
"LL cache accesses": 483313,
|
||
|
"L2D TLB accesses": 134440,
|
||
|
"L2D TLB misses": 17618,
|
||
|
"L2D cache misses": 247222,
|
||
|
"L2D cache accesses": 1452336,
|
||
|
"\u0394 watt": 17.98933333333333,
|
||
|
"branch miss rate": 0.018811288645806598,
|
||
|
"ITLB miss rate": 0.0002122509852186112,
|
||
|
"DTLB miss rate": 0.0003866674532429324,
|
||
|
"L1I cache miss rate": 0.008595751959513315,
|
||
|
"L1D cache miss rate": 0.013435325914798606,
|
||
|
"L2D cache miss rate": 0.17022369479238963,
|
||
|
"LL cache miss rate": 0.9584368721718638
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell48",
|
||
|
"maxwell size": 48,
|
||
|
"matrix columns": 345744,
|
||
|
"task clock (msec)": 34.94,
|
||
|
"page faults": 2771,
|
||
|
"cycles": 38735018,
|
||
|
"instructions": 75159781,
|
||
|
"branch mispredictions": 315149,
|
||
|
"branches": 16816929,
|
||
|
"ITLB accesses": 22633453,
|
||
|
"ITLB misses": 5768,
|
||
|
"DTLB misses": 12591,
|
||
|
"DTLB accesses": 30399400,
|
||
|
"L1I cache accesses": 26918987,
|
||
|
"L1I cache misses": 244722,
|
||
|
"L1D cache misses": 389557,
|
||
|
"L1D cache accesses": 28286479,
|
||
|
"LL cache misses": 462508,
|
||
|
"LL cache accesses": 481919,
|
||
|
"L2D TLB accesses": 136590,
|
||
|
"L2D TLB misses": 17961,
|
||
|
"L2D cache misses": 246707,
|
||
|
"L2D cache accesses": 1437179,
|
||
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"\u0394 watt": 12.584000000000003,
|
||
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|
||
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|
||
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|
||
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"L1I cache miss rate": 0.009091055320915307,
|
||
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"L1D cache miss rate": 0.013771844845022953,
|
||
|
"L2D cache miss rate": 0.17166059342642775,
|
||
|
"LL cache miss rate": 0.9597214469651539
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell34",
|
||
|
"maxwell size": 34,
|
||
|
"matrix columns": 124950,
|
||
|
"task clock (msec)": 31.77,
|
||
|
"page faults": 2772,
|
||
|
"cycles": 21933963,
|
||
|
"instructions": 71670947,
|
||
|
"branch mispredictions": 313067,
|
||
|
"branches": 16949851,
|
||
|
"ITLB accesses": 22410986,
|
||
|
"ITLB misses": 5228,
|
||
|
"DTLB misses": 12020,
|
||
|
"DTLB accesses": 30113343,
|
||
|
"L1I cache accesses": 26523000,
|
||
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"L1I cache misses": 232921,
|
||
|
"L1D cache misses": 380346,
|
||
|
"L1D cache accesses": 27768454,
|
||
|
"LL cache misses": 470177,
|
||
|
"LL cache accesses": 493751,
|
||
|
"L2D TLB accesses": 134281,
|
||
|
"L2D TLB misses": 16783,
|
||
|
"L2D cache misses": 257166,
|
||
|
"L2D cache accesses": 1461513,
|
||
|
"\u0394 watt": 17.726666666666663,
|
||
|
"branch miss rate": 0.018470191861863564,
|
||
|
"ITLB miss rate": 0.00023327844656187817,
|
||
|
"DTLB miss rate": 0.0003991586055390795,
|
||
|
"L1I cache miss rate": 0.008781849715341402,
|
||
|
"L1D cache miss rate": 0.013697053498188987,
|
||
|
"L2D cache miss rate": 0.17595874959716404,
|
||
|
"LL cache miss rate": 0.9522552865715715
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell44",
|
||
|
"maxwell size": 44,
|
||
|
"matrix columns": 267300,
|
||
|
"task clock (msec)": 33.08,
|
||
|
"page faults": 2779,
|
||
|
"cycles": 25039508,
|
||
|
"instructions": 73874444,
|
||
|
"branch mispredictions": 314391,
|
||
|
"branches": 16756549,
|
||
|
"ITLB accesses": 22832236,
|
||
|
"ITLB misses": 5366,
|
||
|
"DTLB misses": 12776,
|
||
|
"DTLB accesses": 30548671,
|
||
|
"L1I cache accesses": 26617695,
|
||
|
"L1I cache misses": 251490,
|
||
|
"L1D cache misses": 393877,
|
||
|
"L1D cache accesses": 27768409,
|
||
|
"LL cache misses": 473559,
|
||
|
"LL cache accesses": 506336,
|
||
|
"L2D TLB accesses": 138392,
|
||
|
"L2D TLB misses": 18953,
|
||
|
"L2D cache misses": 267893,
|
||
|
"L2D cache accesses": 1496868,
|
||
|
"\u0394 watt": 13.570666666666668,
|
||
|
"branch miss rate": 0.018762276170349874,
|
||
|
"ITLB miss rate": 0.00023501859388629304,
|
||
|
"DTLB miss rate": 0.0004182178661716577,
|
||
|
"L1I cache miss rate": 0.009448226076675685,
|
||
|
"L1D cache miss rate": 0.014184356042868714,
|
||
|
"L2D cache miss rate": 0.1789690206484473,
|
||
|
"LL cache miss rate": 0.9352663053782468
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell30",
|
||
|
"maxwell size": 30,
|
||
|
"matrix columns": 86490,
|
||
|
"task clock (msec)": 30.87,
|
||
|
"page faults": 2759,
|
||
|
"cycles": 37012840,
|
||
|
"instructions": 73960783,
|
||
|
"branch mispredictions": 315756,
|
||
|
"branches": 16812678,
|
||
|
"ITLB accesses": 22882240,
|
||
|
"ITLB misses": 5700,
|
||
|
"DTLB misses": 12892,
|
||
|
"DTLB accesses": 30639838,
|
||
|
"L1I cache accesses": 26461356,
|
||
|
"L1I cache misses": 231196,
|
||
|
"L1D cache misses": 378676,
|
||
|
"L1D cache accesses": 27671660,
|
||
|
"LL cache misses": 470732,
|
||
|
"LL cache accesses": 496250,
|
||
|
"L2D TLB accesses": 135873,
|
||
|
"L2D TLB misses": 19574,
|
||
|
"L2D cache misses": 261795,
|
||
|
"L2D cache accesses": 1476352,
|
||
|
"\u0394 watt": 9.581333333333337,
|
||
|
"branch miss rate": 0.01878082718291518,
|
||
|
"ITLB miss rate": 0.0002491014865677486,
|
||
|
"DTLB miss rate": 0.00042075940479841965,
|
||
|
"L1I cache miss rate": 0.008737118385013981,
|
||
|
"L1D cache miss rate": 0.013684614511742339,
|
||
|
"L2D cache miss rate": 0.1773255971475637,
|
||
|
"LL cache miss rate": 0.9485783375314861
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell30",
|
||
|
"maxwell size": 30,
|
||
|
"matrix columns": 86490,
|
||
|
"task clock (msec)": 38.13,
|
||
|
"page faults": 2794,
|
||
|
"cycles": 32415571,
|
||
|
"instructions": 75634143,
|
||
|
"branch mispredictions": 312624,
|
||
|
"branches": 16735629,
|
||
|
"ITLB accesses": 22746815,
|
||
|
"ITLB misses": 5116,
|
||
|
"DTLB misses": 12449,
|
||
|
"DTLB accesses": 30413011,
|
||
|
"L1I cache accesses": 26672713,
|
||
|
"L1I cache misses": 231027,
|
||
|
"L1D cache misses": 377361,
|
||
|
"L1D cache accesses": 27757160,
|
||
|
"LL cache misses": 469460,
|
||
|
"LL cache accesses": 493233,
|
||
|
"L2D TLB accesses": 136380,
|
||
|
"L2D TLB misses": 18404,
|
||
|
"L2D cache misses": 255871,
|
||
|
"L2D cache accesses": 1460513,
|
||
|
"\u0394 watt": 17.996,
|
||
|
"branch miss rate": 0.018680146410989393,
|
||
|
"ITLB miss rate": 0.00022491060836429187,
|
||
|
"DTLB miss rate": 0.00040933138780635693,
|
||
|
"L1I cache miss rate": 0.008661548602123826,
|
||
|
"L1D cache miss rate": 0.013595086817239227,
|
||
|
"L2D cache miss rate": 0.17519255220597146,
|
||
|
"LL cache miss rate": 0.9518016839911361
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell4",
|
||
|
"maxwell size": 4,
|
||
|
"matrix columns": 300,
|
||
|
"task clock (msec)": 31.1,
|
||
|
"page faults": 3260,
|
||
|
"cycles": 49512609,
|
||
|
"instructions": 79157466,
|
||
|
"branches": 17163022,
|
||
|
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|
||
|
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|
||
|
"ITLB misses": 13125,
|
||
|
"DTLB accesses": 17723474,
|
||
|
"DTLB misses": 13123,
|
||
|
"L1D cache accesses": 17642308,
|
||
|
"L1D cache misses": 578691,
|
||
|
"LL cache accesses": 70574,
|
||
|
"LL cache misses": 30238,
|
||
|
"branch miss rate": 0.017288563750602896,
|
||
|
"ITLB miss rate": 1.647627416520211,
|
||
|
"DTLB miss rate": 0.0007404304596265946,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.032801320552843766,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.42845807237792954
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell18",
|
||
|
"maxwell size": 18,
|
||
|
"matrix columns": 19494,
|
||
|
"task clock (msec)": 37.94,
|
||
|
"page faults": 2766,
|
||
|
"cycles": 38331378,
|
||
|
"instructions": 70059972,
|
||
|
"branch mispredictions": 313098,
|
||
|
"branches": 16918712,
|
||
|
"ITLB accesses": 22604179,
|
||
|
"ITLB misses": 5034,
|
||
|
"DTLB misses": 12111,
|
||
|
"DTLB accesses": 30294479,
|
||
|
"L1I cache accesses": 26278079,
|
||
|
"L1I cache misses": 221462,
|
||
|
"L1D cache misses": 380684,
|
||
|
"L1D cache accesses": 27551821,
|
||
|
"LL cache misses": 466481,
|
||
|
"LL cache accesses": 490057,
|
||
|
"L2D TLB accesses": 134286,
|
||
|
"L2D TLB misses": 18651,
|
||
|
"L2D cache misses": 255806,
|
||
|
"L2D cache accesses": 1444473,
|
||
|
"\u0394 watt": 9.651999999999994,
|
||
|
"branch miss rate": 0.01850601866146785,
|
||
|
"ITLB miss rate": 0.00022270218263622846,
|
||
|
"DTLB miss rate": 0.00039977581393626214,
|
||
|
"L1I cache miss rate": 0.008427632780919793,
|
||
|
"L1D cache miss rate": 0.01381701775719289,
|
||
|
"L2D cache miss rate": 0.1770929605468569,
|
||
|
"LL cache miss rate": 0.9518913106026442
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell8",
|
||
|
"maxwell size": 8,
|
||
|
"matrix columns": 1944,
|
||
|
"task clock (msec)": 34.09,
|
||
|
"page faults": 2782,
|
||
|
"cycles": 37064169,
|
||
|
"instructions": 74037049,
|
||
|
"branch mispredictions": 313553,
|
||
|
"branches": 16971332,
|
||
|
"ITLB accesses": 22830212,
|
||
|
"ITLB misses": 5471,
|
||
|
"DTLB misses": 12426,
|
||
|
"DTLB accesses": 30661633,
|
||
|
"L1I cache accesses": 26615111,
|
||
|
"L1I cache misses": 230524,
|
||
|
"L1D cache misses": 376346,
|
||
|
"L1D cache accesses": 27931850,
|
||
|
"LL cache misses": 461499,
|
||
|
"LL cache accesses": 488022,
|
||
|
"L2D TLB accesses": 135124,
|
||
|
"L2D TLB misses": 18143,
|
||
|
"L2D cache misses": 253051,
|
||
|
"L2D cache accesses": 1454207,
|
||
|
"\u0394 watt": 2.6693333333333378,
|
||
|
"branch miss rate": 0.01847545024751151,
|
||
|
"ITLB miss rate": 0.0002396385981873493,
|
||
|
"DTLB miss rate": 0.00040526217243549946,
|
||
|
"L1I cache miss rate": 0.008661395400530172,
|
||
|
"L1D cache miss rate": 0.013473722649949789,
|
||
|
"L2D cache miss rate": 0.1740130531623077,
|
||
|
"LL cache miss rate": 0.9456520402768728
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell26",
|
||
|
"maxwell size": 26,
|
||
|
"matrix columns": 56862,
|
||
|
"task clock (msec)": 35.49,
|
||
|
"page faults": 2781,
|
||
|
"cycles": 35904207,
|
||
|
"instructions": 74255441,
|
||
|
"branch mispredictions": 315604,
|
||
|
"branches": 16831247,
|
||
|
"ITLB accesses": 23016221,
|
||
|
"ITLB misses": 5250,
|
||
|
"DTLB misses": 12426,
|
||
|
"DTLB accesses": 30958111,
|
||
|
"L1I cache accesses": 26467387,
|
||
|
"L1I cache misses": 233063,
|
||
|
"L1D cache misses": 384211,
|
||
|
"L1D cache accesses": 27694892,
|
||
|
"LL cache misses": 464776,
|
||
|
"LL cache accesses": 484199,
|
||
|
"L2D TLB accesses": 134303,
|
||
|
"L2D TLB misses": 18242,
|
||
|
"L2D cache misses": 249032,
|
||
|
"L2D cache accesses": 1443567,
|
||
|
"\u0394 watt": 9.132000000000001,
|
||
|
"branch miss rate": 0.018751076494807544,
|
||
|
"ITLB miss rate": 0.00022809999956117905,
|
||
|
"DTLB miss rate": 0.00040138107909749404,
|
||
|
"L1I cache miss rate": 0.008805667140469892,
|
||
|
"L1D cache miss rate": 0.013872991452719873,
|
||
|
"L2D cache miss rate": 0.17251156337045664,
|
||
|
"LL cache miss rate": 0.9598863277288884
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell44",
|
||
|
"maxwell size": 44,
|
||
|
"matrix columns": 267300,
|
||
|
"task clock (msec)": 30.91,
|
||
|
"page faults": 2746,
|
||
|
"cycles": 33264810,
|
||
|
"instructions": 69273601,
|
||
|
"branch mispredictions": 315526,
|
||
|
"branches": 16760967,
|
||
|
"ITLB accesses": 22949528,
|
||
|
"ITLB misses": 5982,
|
||
|
"DTLB misses": 13101,
|
||
|
"DTLB accesses": 30809060,
|
||
|
"L1I cache accesses": 26535815,
|
||
|
"L1I cache misses": 240994,
|
||
|
"L1D cache misses": 384916,
|
||
|
"L1D cache accesses": 27816607,
|
||
|
"LL cache misses": 460494,
|
||
|
"LL cache accesses": 481127,
|
||
|
"L2D TLB accesses": 132497,
|
||
|
"L2D TLB misses": 18586,
|
||
|
"L2D cache misses": 246736,
|
||
|
"L2D cache accesses": 1446914,
|
||
|
"\u0394 watt": 18.18533333333333,
|
||
|
"branch miss rate": 0.01882504750471736,
|
||
|
"ITLB miss rate": 0.0002606589556003069,
|
||
|
"DTLB miss rate": 0.00042523205836205325,
|
||
|
"L1I cache miss rate": 0.009081839016438727,
|
||
|
"L1D cache miss rate": 0.013837633036983986,
|
||
|
"L2D cache miss rate": 0.1705256843184875,
|
||
|
"LL cache miss rate": 0.9571152730983711
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell42",
|
||
|
"maxwell size": 42,
|
||
|
"matrix columns": 232974,
|
||
|
"task clock (msec)": 34.51,
|
||
|
"page faults": 2760,
|
||
|
"cycles": 35380085,
|
||
|
"instructions": 74882678,
|
||
|
"branch mispredictions": 314478,
|
||
|
"branches": 16924367,
|
||
|
"ITLB accesses": 22759319,
|
||
|
"ITLB misses": 5648,
|
||
|
"DTLB misses": 12671,
|
||
|
"DTLB accesses": 30491137,
|
||
|
"L1I cache accesses": 26636435,
|
||
|
"L1I cache misses": 235128,
|
||
|
"L1D cache misses": 384387,
|
||
|
"L1D cache accesses": 27971398,
|
||
|
"LL cache misses": 465165,
|
||
|
"LL cache accesses": 484747,
|
||
|
"L2D TLB accesses": 132302,
|
||
|
"L2D TLB misses": 17635,
|
||
|
"L2D cache misses": 248647,
|
||
|
"L2D cache accesses": 1440208,
|
||
|
"\u0394 watt": 18.493333333333336,
|
||
|
"branch miss rate": 0.018581374417134772,
|
||
|
"ITLB miss rate": 0.000248162082529798,
|
||
|
"DTLB miss rate": 0.0004155633815819987,
|
||
|
"L1I cache miss rate": 0.008827307408067184,
|
||
|
"L1D cache miss rate": 0.013742144743712846,
|
||
|
"L2D cache miss rate": 0.1726465899370091,
|
||
|
"LL cache miss rate": 0.9596036695430812
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell16",
|
||
|
"maxwell size": 16,
|
||
|
"matrix columns": 13872,
|
||
|
"task clock (msec)": 35.58,
|
||
|
"page faults": 2792,
|
||
|
"cycles": 28042392,
|
||
|
"instructions": 75410629,
|
||
|
"branch mispredictions": 313846,
|
||
|
"branches": 16941333,
|
||
|
"ITLB accesses": 22593698,
|
||
|
"ITLB misses": 5385,
|
||
|
"DTLB misses": 12202,
|
||
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"DTLB accesses": 30439426,
|
||
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"L1I cache accesses": 26430404,
|
||
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"L1I cache misses": 229508,
|
||
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"L1D cache misses": 380816,
|
||
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"L1D cache accesses": 27753131,
|
||
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"LL cache misses": 457586,
|
||
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"LL cache accesses": 478259,
|
||
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"L2D TLB accesses": 132482,
|
||
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"L2D TLB misses": 17723,
|
||
|
"L2D cache misses": 242435,
|
||
|
"L2D cache accesses": 1426434,
|
||
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|
||
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"branch miss rate": 0.018525460776905808,
|
||
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|
||
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|
||
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"L1I cache miss rate": 0.008683484368986565,
|
||
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"L1D cache miss rate": 0.013721550912579917,
|
||
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|
||
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"LL cache miss rate": 0.9567744673910998
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell40",
|
||
|
"maxwell size": 40,
|
||
|
"matrix columns": 201720,
|
||
|
"task clock (msec)": 31.72,
|
||
|
"page faults": 2785,
|
||
|
"cycles": 30090507,
|
||
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"instructions": 74992863,
|
||
|
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|
||
|
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|
||
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|
||
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"ITLB misses": 5557,
|
||
|
"DTLB misses": 12446,
|
||
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"DTLB accesses": 30413594,
|
||
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"L1I cache accesses": 26843425,
|
||
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"L1I cache misses": 239555,
|
||
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"L1D cache misses": 385295,
|
||
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"L1D cache accesses": 27801251,
|
||
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"LL cache misses": 476478,
|
||
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"LL cache accesses": 505239,
|
||
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"L2D TLB accesses": 136570,
|
||
|
"L2D TLB misses": 19385,
|
||
|
"L2D cache misses": 267638,
|
||
|
"L2D cache accesses": 1488002,
|
||
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"\u0394 watt": 12.689333333333337,
|
||
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|
||
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|
||
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|
||
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|
||
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"L1D cache miss rate": 0.013858908723208175,
|
||
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"L2D cache miss rate": 0.17986400555913232,
|
||
|
"LL cache miss rate": 0.9430744657478936
|
||
|
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell14",
|
||
|
"maxwell size": 14,
|
||
|
"matrix columns": 9450,
|
||
|
"task clock (msec)": 34.04,
|
||
|
"page faults": 3255,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 13929,
|
||
|
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|
||
|
"DTLB misses": 12504,
|
||
|
"L1D cache accesses": 17720101,
|
||
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"L1D cache misses": 590640,
|
||
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"LL cache accesses": 79901,
|
||
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|
||
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|
||
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|
||
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"DTLB miss rate": 0.0007029571875236118,
|
||
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"L1I cache miss rate": null,
|
||
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|
||
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"L2D cache miss rate": null,
|
||
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"LL cache miss rate": 0.352348531307493
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell14",
|
||
|
"maxwell size": 14,
|
||
|
"matrix columns": 9450,
|
||
|
"task clock (msec)": 32.29,
|
||
|
"page faults": 2770,
|
||
|
"cycles": 24172523,
|
||
|
"instructions": 55925355,
|
||
|
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|
||
|
"branches": 16867022,
|
||
|
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|
||
|
"ITLB misses": 5397,
|
||
|
"DTLB misses": 12729,
|
||
|
"DTLB accesses": 30412650,
|
||
|
"L1I cache accesses": 26252660,
|
||
|
"L1I cache misses": 230453,
|
||
|
"L1D cache misses": 372224,
|
||
|
"L1D cache accesses": 27429044,
|
||
|
"LL cache misses": 468447,
|
||
|
"LL cache accesses": 497410,
|
||
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"L2D TLB accesses": 134272,
|
||
|
"L2D TLB misses": 17416,
|
||
|
"L2D cache misses": 260097,
|
||
|
"L2D cache accesses": 1447346,
|
||
|
"\u0394 watt": 2.3826666666666654,
|
||
|
"branch miss rate": 0.018767865483308197,
|
||
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"ITLB miss rate": 0.00023748734951928944,
|
||
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|
||
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"L1I cache miss rate": 0.008778272373161424,
|
||
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"L1D cache miss rate": 0.013570432859417192,
|
||
|
"L2D cache miss rate": 0.17970616563005667,
|
||
|
"LL cache miss rate": 0.9417723809332341
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell6",
|
||
|
"maxwell size": 6,
|
||
|
"matrix columns": 882,
|
||
|
"task clock (msec)": 40.34,
|
||
|
"page faults": 2792,
|
||
|
"cycles": 40725361,
|
||
|
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|
||
|
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|
||
|
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||
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||
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|
||
|
"DTLB misses": 12545,
|
||
|
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|
||
|
"L1I cache accesses": 26633420,
|
||
|
"L1I cache misses": 229672,
|
||
|
"L1D cache misses": 383161,
|
||
|
"L1D cache accesses": 27956131,
|
||
|
"LL cache misses": 463797,
|
||
|
"LL cache accesses": 489201,
|
||
|
"L2D TLB accesses": 135365,
|
||
|
"L2D TLB misses": 18059,
|
||
|
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|
||
|
"L2D cache accesses": 1489942,
|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
|
"L1D cache miss rate": 0.013705794982860826,
|
||
|
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|
||
|
"LL cache miss rate": 0.9480704250400143
|
||
|
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell8",
|
||
|
"maxwell size": 8,
|
||
|
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|
||
|
"task clock (msec)": 27.37,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache accesses": 17644914,
|
||
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"L1D cache misses": 585931,
|
||
|
"LL cache accesses": 63994,
|
||
|
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|
||
|
"branch miss rate": 0.01712870050420343,
|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.03320679262024173,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.17992311779229303
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell42",
|
||
|
"maxwell size": 42,
|
||
|
"matrix columns": 232974,
|
||
|
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|
||
|
"page faults": 2767,
|
||
|
"cycles": 36494687,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
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|
||
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|
||
|
"L1I cache misses": 231708,
|
||
|
"L1D cache misses": 380332,
|
||
|
"L1D cache accesses": 27654763,
|
||
|
"LL cache misses": 463631,
|
||
|
"LL cache accesses": 486406,
|
||
|
"L2D TLB accesses": 135704,
|
||
|
"L2D TLB misses": 17865,
|
||
|
"L2D cache misses": 252089,
|
||
|
"L2D cache accesses": 1453983,
|
||
|
"\u0394 watt": 10.441333333333336,
|
||
|
"branch miss rate": 0.01890426589727289,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013752856967170537,
|
||
|
"L2D cache miss rate": 0.17337823069458172,
|
||
|
"LL cache miss rate": 0.9531769756129653
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell8",
|
||
|
"maxwell size": 8,
|
||
|
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|
||
|
"task clock (msec)": 31.43,
|
||
|
"page faults": 2786,
|
||
|
"cycles": 32825625,
|
||
|
"instructions": 75014125,
|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 385270,
|
||
|
"L1D cache accesses": 27778791,
|
||
|
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|
||
|
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|
||
|
"L2D TLB accesses": 130326,
|
||
|
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|
||
|
"L2D cache misses": 244717,
|
||
|
"L2D cache accesses": 1437795,
|
||
|
"\u0394 watt": 2.287999999999993,
|
||
|
"branch miss rate": 0.01864763546818545,
|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": 0.008801200150290232,
|
||
|
"L1D cache miss rate": 0.013869214106546249,
|
||
|
"L2D cache miss rate": 0.1702029844310211,
|
||
|
"LL cache miss rate": 0.9561995896566905
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell16",
|
||
|
"maxwell size": 16,
|
||
|
"matrix columns": 13872,
|
||
|
"task clock (msec)": 32.1,
|
||
|
"page faults": 3258,
|
||
|
"cycles": 52669502,
|
||
|
"instructions": 78956410,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 13925,
|
||
|
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|
||
|
"DTLB misses": 13397,
|
||
|
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|
||
|
"L1D cache misses": 585596,
|
||
|
"LL cache accesses": 63570,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.0330767308579539,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.345996539248073
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell36",
|
||
|
"maxwell size": 36,
|
||
|
"matrix columns": 147852,
|
||
|
"task clock (msec)": 33.27,
|
||
|
"page faults": 2753,
|
||
|
"cycles": 35426575,
|
||
|
"instructions": 71870191,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache misses": 239661,
|
||
|
"L1D cache misses": 388417,
|
||
|
"L1D cache accesses": 28077546,
|
||
|
"LL cache misses": 470825,
|
||
|
"LL cache accesses": 499788,
|
||
|
"L2D TLB accesses": 134784,
|
||
|
"L2D TLB misses": 17541,
|
||
|
"L2D cache misses": 259055,
|
||
|
"L2D cache accesses": 1481192,
|
||
|
"\u0394 watt": 18.52133333333333,
|
||
|
"branch miss rate": 0.018828051870368182,
|
||
|
"ITLB miss rate": 0.00026035514306534905,
|
||
|
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|
||
|
"L1I cache miss rate": 0.008951735793194027,
|
||
|
"L1D cache miss rate": 0.013833723217833924,
|
||
|
"L2D cache miss rate": 0.1748962997369686,
|
||
|
"LL cache miss rate": 0.9420494289578781
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell18",
|
||
|
"maxwell size": 18,
|
||
|
"matrix columns": 19494,
|
||
|
"task clock (msec)": 30.27,
|
||
|
"page faults": 2770,
|
||
|
"cycles": 50550862,
|
||
|
"instructions": 79719924,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"ITLB misses": 13736,
|
||
|
"DTLB accesses": 17549541,
|
||
|
"DTLB misses": 12086,
|
||
|
"L1D cache accesses": 18242451,
|
||
|
"L1D cache misses": 585771,
|
||
|
"LL cache accesses": 74593,
|
||
|
"LL cache misses": 27394,
|
||
|
"branch miss rate": 0.017180042846662386,
|
||
|
"ITLB miss rate": 1.9302979201798762,
|
||
|
"DTLB miss rate": 0.0006886789802650679,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.03211032333319684,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.3672462563511321
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell4",
|
||
|
"maxwell size": 4,
|
||
|
"matrix columns": 300,
|
||
|
"task clock (msec)": 36.52,
|
||
|
"page faults": 2774,
|
||
|
"cycles": 27452119,
|
||
|
"instructions": 75842779,
|
||
|
"branch mispredictions": 310172,
|
||
|
"branches": 16670816,
|
||
|
"ITLB accesses": 22606324,
|
||
|
"ITLB misses": 4704,
|
||
|
"DTLB misses": 11949,
|
||
|
"DTLB accesses": 30316550,
|
||
|
"L1I cache accesses": 26555286,
|
||
|
"L1I cache misses": 223942,
|
||
|
"L1D cache misses": 370100,
|
||
|
"L1D cache accesses": 27948620,
|
||
|
"LL cache misses": 457578,
|
||
|
"LL cache accesses": 478311,
|
||
|
"L2D TLB accesses": 133288,
|
||
|
"L2D TLB misses": 16236,
|
||
|
"L2D cache misses": 243738,
|
||
|
"L2D cache accesses": 1421114,
|
||
|
"\u0394 watt": 3.8346666666666636,
|
||
|
"branch miss rate": 0.018605687927933462,
|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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"cpu": "xeon",
|
||
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|
||
|
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|
||
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"input file": "maxwell18",
|
||
|
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|
||
|
"matrix columns": 19494,
|
||
|
"task clock (msec)": 27.88,
|
||
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"page faults": 2760,
|
||
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"cycles": 46921016,
|
||
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|
||
|
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|
||
|
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|
||
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|
||
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"ITLB misses": 14952,
|
||
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|
||
|
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|
||
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|
||
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"L1D cache misses": 588225,
|
||
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|
||
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|
||
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"branch miss rate": 0.017099362249329945,
|
||
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|
||
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|
||
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"L1I cache miss rate": null,
|
||
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|
||
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"L2D cache miss rate": null,
|
||
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|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
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"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell38",
|
||
|
"maxwell size": 38,
|
||
|
"matrix columns": 173394,
|
||
|
"task clock (msec)": 38.61,
|
||
|
"page faults": 2766,
|
||
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"cycles": 39328079,
|
||
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|
||
|
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|
||
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|
||
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|
||
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"ITLB misses": 5189,
|
||
|
"DTLB misses": 12161,
|
||
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|
||
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|
||
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"L1I cache misses": 229528,
|
||
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"L1D cache misses": 378890,
|
||
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"L1D cache accesses": 27541548,
|
||
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"LL cache misses": 463900,
|
||
|
"LL cache accesses": 489009,
|
||
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"L2D TLB accesses": 134701,
|
||
|
"L2D TLB misses": 18706,
|
||
|
"L2D cache misses": 254272,
|
||
|
"L2D cache accesses": 1461379,
|
||
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|
||
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"branch miss rate": 0.0183733906578427,
|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
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|
||
|
"cpu": "xeon",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell8",
|
||
|
"maxwell size": 8,
|
||
|
"matrix columns": 1944,
|
||
|
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|
||
|
"page faults": 2725,
|
||
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"cycles": 44632551,
|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache accesses": 17635810,
|
||
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"L1D cache misses": 580270,
|
||
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|
||
|
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|
||
|
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|
||
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"ITLB miss rate": 1.9597567287784678,
|
||
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|
||
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|
||
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|
||
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"L2D cache miss rate": null,
|
||
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"LL cache miss rate": 0.15873579545454544
|
||
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell4",
|
||
|
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|
||
|
"matrix columns": 300,
|
||
|
"task clock (msec)": 28.86,
|
||
|
"page faults": 3264,
|
||
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"cycles": 46795526,
|
||
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|
||
|
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|
||
|
"branch mispredictions": 298327,
|
||
|
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|
||
|
"ITLB misses": 14795,
|
||
|
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|
||
|
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|
||
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"L1D cache accesses": 17505349,
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||
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"L1D cache misses": 581950,
|
||
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"LL cache accesses": 64296,
|
||
|
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|
||
|
"branch miss rate": 0.017456091779720666,
|
||
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"ITLB miss rate": 1.9523621008181578,
|
||
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"DTLB miss rate": 0.000793010905213619,
|
||
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"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.033244124410201706,
|
||
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"L2D cache miss rate": null,
|
||
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"LL cache miss rate": 0.16920181659823316
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell46",
|
||
|
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|
||
|
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|
||
|
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|
||
|
"page faults": 2767,
|
||
|
"cycles": 22305313,
|
||
|
"instructions": 76129183,
|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache accesses": 26439331,
|
||
|
"L1I cache misses": 237296,
|
||
|
"L1D cache misses": 383050,
|
||
|
"L1D cache accesses": 27780593,
|
||
|
"LL cache misses": 466156,
|
||
|
"LL cache accesses": 496369,
|
||
|
"L2D TLB accesses": 136658,
|
||
|
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|
||
|
"L2D cache misses": 257674,
|
||
|
"L2D cache accesses": 1463558,
|
||
|
"\u0394 watt": 18.817333333333327,
|
||
|
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|
||
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013788402572976035,
|
||
|
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|
||
|
"LL cache miss rate": 0.9391319764127091
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell44",
|
||
|
"maxwell size": 44,
|
||
|
"matrix columns": 267300,
|
||
|
"task clock (msec)": 36.17,
|
||
|
"page faults": 2781,
|
||
|
"cycles": 36947128,
|
||
|
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|
||
|
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|
||
|
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||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
"L1D cache misses": 383301,
|
||
|
"L1D cache accesses": 28060808,
|
||
|
"LL cache misses": 465431,
|
||
|
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|
||
|
"L2D TLB accesses": 137926,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"\u0394 watt": 11.313333333333329,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": 0.00894091347617682,
|
||
|
"L1D cache miss rate": 0.013659656557288015,
|
||
|
"L2D cache miss rate": 0.17563677572595818,
|
||
|
"LL cache miss rate": 0.9546832566191613
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell28",
|
||
|
"maxwell size": 28,
|
||
|
"matrix columns": 70644,
|
||
|
"task clock (msec)": 34.62,
|
||
|
"page faults": 2762,
|
||
|
"cycles": 31974608,
|
||
|
"instructions": 73403059,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache misses": 227022,
|
||
|
"L1D cache misses": 373950,
|
||
|
"L1D cache accesses": 27566086,
|
||
|
"LL cache misses": 469059,
|
||
|
"LL cache accesses": 494454,
|
||
|
"L2D TLB accesses": 137297,
|
||
|
"L2D TLB misses": 17492,
|
||
|
"L2D cache misses": 256015,
|
||
|
"L2D cache accesses": 1464510,
|
||
|
"\u0394 watt": 8.707999999999995,
|
||
|
"branch miss rate": 0.018607545299686112,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache miss rate": 0.013565581998111738,
|
||
|
"L2D cache miss rate": 0.174812736000437,
|
||
|
"LL cache miss rate": 0.948640318411824
|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell10",
|
||
|
"maxwell size": 10,
|
||
|
"matrix columns": 3630,
|
||
|
"task clock (msec)": 36.02,
|
||
|
"page faults": 2754,
|
||
|
"cycles": 28216835,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"DTLB misses": 13349,
|
||
|
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|
||
|
"L1I cache accesses": 26592108,
|
||
|
"L1I cache misses": 231135,
|
||
|
"L1D cache misses": 376017,
|
||
|
"L1D cache accesses": 27882306,
|
||
|
"LL cache misses": 442447,
|
||
|
"LL cache accesses": 466619,
|
||
|
"L2D TLB accesses": 159723,
|
||
|
"L2D TLB misses": 20452,
|
||
|
"L2D cache misses": 246420,
|
||
|
"L2D cache accesses": 1483875,
|
||
|
"\u0394 watt": 4.84,
|
||
|
"branch miss rate": 0.018509508016739527,
|
||
|
"ITLB miss rate": 0.0002736100338410808,
|
||
|
"DTLB miss rate": 0.0004317706335031629,
|
||
|
"L1I cache miss rate": 0.008691864518600783,
|
||
|
"L1D cache miss rate": 0.01348586447620222,
|
||
|
"L2D cache miss rate": 0.16606520090978014,
|
||
|
"LL cache miss rate": 0.9481975658942307
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell22",
|
||
|
"maxwell size": 22,
|
||
|
"matrix columns": 34914,
|
||
|
"task clock (msec)": 40.05,
|
||
|
"page faults": 2787,
|
||
|
"cycles": 35617476,
|
||
|
"instructions": 70762281,
|
||
|
"branch mispredictions": 315551,
|
||
|
"branches": 17092160,
|
||
|
"ITLB accesses": 22270930,
|
||
|
"ITLB misses": 5115,
|
||
|
"DTLB misses": 12145,
|
||
|
"DTLB accesses": 29954782,
|
||
|
"L1I cache accesses": 26790202,
|
||
|
"L1I cache misses": 235685,
|
||
|
"L1D cache misses": 385839,
|
||
|
"L1D cache accesses": 28190052,
|
||
|
"LL cache misses": 463555,
|
||
|
"LL cache accesses": 488806,
|
||
|
"L2D TLB accesses": 132085,
|
||
|
"L2D TLB misses": 17078,
|
||
|
"L2D cache misses": 248234,
|
||
|
"L2D cache accesses": 1456769,
|
||
|
"\u0394 watt": 5.119999999999997,
|
||
|
"branch miss rate": 0.01846173918334488,
|
||
|
"ITLB miss rate": 0.0002296715943159985,
|
||
|
"DTLB miss rate": 0.00040544444623232445,
|
||
|
"L1I cache miss rate": 0.00879743273305666,
|
||
|
"L1D cache miss rate": 0.01368706237221556,
|
||
|
"L2D cache miss rate": 0.17040038605983515,
|
||
|
"LL cache miss rate": 0.9483414688035744
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell24",
|
||
|
"maxwell size": 24,
|
||
|
"matrix columns": 45000,
|
||
|
"task clock (msec)": 32.53,
|
||
|
"page faults": 2785,
|
||
|
"cycles": 29159609,
|
||
|
"instructions": 70314265,
|
||
|
"branch mispredictions": 316033,
|
||
|
"branches": 16873830,
|
||
|
"ITLB accesses": 23069521,
|
||
|
"ITLB misses": 5362,
|
||
|
"DTLB misses": 12762,
|
||
|
"DTLB accesses": 30842612,
|
||
|
"L1I cache accesses": 26686872,
|
||
|
"L1I cache misses": 224715,
|
||
|
"L1D cache misses": 377368,
|
||
|
"L1D cache accesses": 28139495,
|
||
|
"LL cache misses": 474128,
|
||
|
"LL cache accesses": 497388,
|
||
|
"L2D TLB accesses": 133601,
|
||
|
"L2D TLB misses": 18428,
|
||
|
"L2D cache misses": 255989,
|
||
|
"L2D cache accesses": 1466756,
|
||
|
"\u0394 watt": 17.632,
|
||
|
"branch miss rate": 0.018729180037964113,
|
||
|
"ITLB miss rate": 0.0002324278861273279,
|
||
|
"DTLB miss rate": 0.0004137781845454594,
|
||
|
"L1I cache miss rate": 0.008420432338417182,
|
||
|
"L1D cache miss rate": 0.013410617354717986,
|
||
|
"L2D cache miss rate": 0.174527324244796,
|
||
|
"LL cache miss rate": 0.9532357033141129
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell28",
|
||
|
"maxwell size": 28,
|
||
|
"matrix columns": 70644,
|
||
|
"task clock (msec)": 34.13,
|
||
|
"page faults": 2773,
|
||
|
"cycles": 34485952,
|
||
|
"instructions": 69695625,
|
||
|
"branch mispredictions": 311099,
|
||
|
"branches": 16943287,
|
||
|
"ITLB accesses": 22528950,
|
||
|
"ITLB misses": 5140,
|
||
|
"DTLB misses": 12133,
|
||
|
"DTLB accesses": 30222074,
|
||
|
"L1I cache accesses": 26470998,
|
||
|
"L1I cache misses": 234215,
|
||
|
"L1D cache misses": 384868,
|
||
|
"L1D cache accesses": 27702279,
|
||
|
"LL cache misses": 460126,
|
||
|
"LL cache accesses": 479561,
|
||
|
"L2D TLB accesses": 130255,
|
||
|
"L2D TLB misses": 17812,
|
||
|
"L2D cache misses": 247457,
|
||
|
"L2D cache accesses": 1447544,
|
||
|
"\u0394 watt": 8.194666666666663,
|
||
|
"branch miss rate": 0.018361195203740573,
|
||
|
"ITLB miss rate": 0.0002281508902989265,
|
||
|
"DTLB miss rate": 0.0004014615277561692,
|
||
|
"L1I cache miss rate": 0.008847985255410468,
|
||
|
"L1D cache miss rate": 0.01389300858604449,
|
||
|
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|
||
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|
||
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|
||
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|
||
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"cpu": "altra",
|
||
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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||
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||
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|
||
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|
||
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||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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"L1D cache accesses": 28434417,
|
||
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"LL cache misses": 466672,
|
||
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|
||
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|
||
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"L2D TLB misses": 18879,
|
||
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|
||
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"L2D cache accesses": 1461320,
|
||
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|
||
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell38",
|
||
|
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|
||
|
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|
||
|
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|
||
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||
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|
||
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|
||
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|
||
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||
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||
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|
||
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|
||
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||
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|
||
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|
||
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||
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||
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
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|
||
|
"input file": "maxwell16",
|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
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||
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|
||
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||
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|
||
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|
||
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|
||
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||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "GMRES",
|
||
|
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|
||
|
"input file": "maxwell20",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
|
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||
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|
||
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|
||
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|
||
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||
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
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|
||
|
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|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "MueLu",
|
||
|
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|
||
|
"input file": "maxwell40",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
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||
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||
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|
||
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||
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|
||
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||
|
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||
|
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||
|
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|
||
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||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
{
|
||
|
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|
||
|
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|
||
|
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|
||
|
"input file": "maxwell20",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
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|
||
|
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|
||
|
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|
||
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||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell18",
|
||
|
"maxwell size": 18,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 379632,
|
||
|
"L1D cache accesses": 28510815,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache misses": 259011,
|
||
|
"L2D cache accesses": 1466702,
|
||
|
"\u0394 watt": 3.5280000000000022,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "GMRES",
|
||
|
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|
||
|
"input file": "maxwell48",
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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||
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|
||
|
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|
||
|
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|
||
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache accesses": 1471965,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L2D cache miss rate": 0.1755021349013054,
|
||
|
"LL cache miss rate": 0.9416130408324589
|
||
|
},
|
||
|
{
|
||
|
"cpu": "altra",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell16",
|
||
|
"maxwell size": 16,
|
||
|
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|
||
|
"task clock (msec)": 32.59,
|
||
|
"page faults": 2776,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1D cache misses": 389567,
|
||
|
"L1D cache accesses": 28166555,
|
||
|
"LL cache misses": 471274,
|
||
|
"LL cache accesses": 499214,
|
||
|
"L2D TLB accesses": 135744,
|
||
|
"L2D TLB misses": 17687,
|
||
|
"L2D cache misses": 261748,
|
||
|
"L2D cache accesses": 1495657,
|
||
|
"\u0394 watt": 2.847999999999999,
|
||
|
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|
||
|
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|
||
|
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|
||
|
"L1I cache miss rate": 0.009349439382414875,
|
||
|
"L1D cache miss rate": 0.013830835897396754,
|
||
|
"L2D cache miss rate": 0.17500536553501236,
|
||
|
"LL cache miss rate": 0.9440320183328192
|
||
|
},
|
||
|
{
|
||
|
"cpu": "xeon",
|
||
|
"solver": "CG",
|
||
|
"linear algebra": "Tpetra",
|
||
|
"input file": "maxwell10",
|
||
|
"maxwell size": 10,
|
||
|
"matrix columns": 3630,
|
||
|
"task clock (msec)": 31.81,
|
||
|
"page faults": 3265,
|
||
|
"cycles": 50932477,
|
||
|
"instructions": 78802385,
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
"DTLB misses": 12396,
|
||
|
"L1D cache accesses": 18127571,
|
||
|
"L1D cache misses": 590459,
|
||
|
"LL cache accesses": 75543,
|
||
|
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|
||
|
"branch miss rate": 0.017078859339524674,
|
||
|
"ITLB miss rate": 1.217345038574089,
|
||
|
"DTLB miss rate": 0.0007010555648180049,
|
||
|
"L1I cache miss rate": null,
|
||
|
"L1D cache miss rate": 0.03257242793311912,
|
||
|
"L2D cache miss rate": null,
|
||
|
"LL cache miss rate": 0.3370927815945885
|
||
|
}
|
||
|
]
|